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参数资料
| 型号： | 9LPRS365BKLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC64 |
| 封装： | PLASTIC, VQFN-64 |
| 文件页数： | 13/28页 |
| 文件大小： | 301K |
| 代理商： | 9LPRS365BKLF |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
20
ICS9LPRS365
Datasheet
1218—09/01/10
Byte 0 FS Readback and PLL Selection Register
Bit
Pin
Name
Description
Type
0
1
Default
7
-
FSLC
CPU Freq. Sel. Bit (Most Significant)
R
Latch
6
-
FSLB
CPU Freq. Sel. Bit
R
Latch
5
-
FSLA
CPU Freq. Sel. Bit (Least Significant)
R
Latch
4-
iAMT_EN
Set via SMBus or dynamically by CK505 if detects
dynamic M1
RW
(Sticky
Bit)
Legacy Mode
iAMT Enabled
0
3
Reserved
RW
0
2
-
SRC_Main_SEL
Select source for SRC Main
RW
SRC Main = PLL1 SRC Main = PLL3
0
1
-
SATA_SEL
Select source for SATA clock
RW
SATA =
SRC_Main
SATA = PLL2
0
0-
PD_Restore
If config saved, on deassert return to last known
state else clear all config as if cold power on and go
to latches open state
RW
Configuration Not
Saved
Configuration
Saved
1
Byte 1 DOT96 Select and PLL3 Quick Config Register
Bit
Pin
Name
Description
Type
0
1
Default
7
13/14
SRC0_SEL
Select SRC0 or DOT96
R
SRC0
DOT96
Note 1
6
-
PLL1_SSC_SEL
Select 0.5% down or center SSC
RW
Down spread
Center spread
0
5Reserved
RW
0
4
17/18
PLL3_CF3
PLL3 Quick Config Bit 3
RW
0
3
PLL3_CF2
PLL3 Quick Config Bit 2
RW
0
2
PLL3_CF1
PLL3 Quick Config Bit 1
RW
1
PLL3_CF0
PLL3 Quick Config Bit 0
RW
0
PCI_SEL
RW
PCI from PLL1
PCI from PLL3
1
Note 1 : When 27_Select pin = 0, B1b7 PWD = 1, , when 27_Select pin = 1, PWD = 0
Byte 2 Output Enable Register
Bit
Pin
Name
Description
Type
0
1
Default
7REF_OE
Output enable for REF, if disabled output is tri-
stated
RW
Output Disabled
Output Enabled
1
6
USB_OE
Output enable for USB
RW
Output Disabled
Output Enabled
1
5
PCIF5_OE
Output enable for PCI5
RW
Output Disabled
Output Enabled
1
4
PCI4_OE
Output enable for PCI4
RW
Output Disabled
Output Enabled
1
3
PCI3_OE
Output enable for PCI3
RW
Output Disabled
Output Enabled
1
2
PCI2_OE
Output enable for PCI2
RW
Output Disabled
Output Enabled
1
PCI1_OE
Output enable for PCI1
RW
Output Disabled
Output Enabled
1
0
PCI0_OE
Output enable for PCI0
RW
Output Disabled
Output Enabled
1
Byte 3 Output Enable Register
Bit
Pin
Name
Description
Type
0
1
Default
7
SRC11_OE
Output enable for SRC11
RW
Output Disabled
Output Enabled
1
6
SRC10_OE
Output enable for SRC10
RW
Output Disabled
Output Enabled
1
5
SRC9_OE
Output enable for SRC9
RW
Output Disabled
Output Enabled
1
4
SRC8/ITP_OE
Output enable for SRC8 or ITP
RW
Output Disabled
Output Enabled
1
3
SRC7_OE
Output enable for SRC7
RW
Output Disabled
Output Enabled
1
2
SRC6_OE
Output enable for SRC6
RW
Output Disabled
Output Enabled
1
Reserved
RW
Output Disabled
Output Enabled
1
0
SRC4_OE
Output enable for SRC4
RW
Output Disabled
Output Enabled
1
See Table 2: pin17, 18 Configuration
Only applies if Byte 0, bit 2 = 0.
See Table 1 : CPU Frequency Select
Table
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