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参数资料
| 型号： | 9LPRS365BKLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC64 |
| 封装： | PLASTIC, VQFN-64 |
| 文件页数： | 18/28页 |
| 文件大小： | 301K |
| 代理商： | 9LPRS365BKLF |
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25
ICS9LPRS365
Datasheet
1218—09/01/10
Test Clarification Table
Comments
FSLC/
TEST_SEL
HW PIN
FSLB/
TEST_MODE
HW PIN
TEST
ENTRY BIT
B9b3
REF/N or
HI-Z
B9b4
OUTPUT
<2.0V
X
0
NORMAL
>2.0V
0
X
0
HI-Z
>2.0V
0
X
1
REF/N
>2.0V
1
X
0
REF/N
>2.0V
1
X
1
REF/N
<2.0V
X
1
0
HI-Z
<2.0V
X
1
REF/N
HW
SW
Power-up w/ TEST_SEL = 1 to enter test mode
Cycle power to disable test mode
FSLC./TEST_SEL -->3-level latched input
If power-up w/ V>2.0V then use TEST_SEL
If power-up w/ V<2.0V then use FSLC
FSLB/TEST_MODE -->low Vth input
TEST_MODE is a real time input
If TEST_SEL HW pin is 0 during power-up,
test mode can be invoked through B9b3.
If test mode is invoked by B9b3, only B9b4
is used to select HI-Z or REF/N
FSLB/TEST_Mode pin is not used.
Cycle power to disable test mode, one shot control
B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B9b4: 1= REF/N, Default = 0 (HI-Z)
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