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参数资料
| 型号： | 9LPRS365BKLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC64 |
| 封装： | PLASTIC, VQFN-64 |
| 文件页数： | 2/28页 |
| 文件大小： | 301K |
| 代理商： | 9LPRS365BKLF |
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10
ICS9LPRS365
Datasheet
1218—09/01/10
MLF Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
49
GNDSRC
PWR
Ground for SRC clocks
50
SRCC7/CR#_E
I/O
SRC7 complement or Clock Request control E for SRC6 pair
The power-up default is SRC7#, but this pin may also be used as a Clock Request control of
SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair
must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte
6, bit 7 of SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_E controls SRC6.
51
SRCT7/CR#_F
I/O
SRC7 true or Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request control of
SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair
must first be disabled in byte 3, bit 3 of SMBus configuration space After the SRC output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC8 pair using byte
6, bit 6 of SMBus configuration space
Byte 6, bit 6
0 = SRC7# enabled (default)
1 = CR#_F controls SRC8.
52
VDDSRC_IO
PWR
1.05V to 3.3V from external power supply
53
CPUC2_ITP/SRCC8
OUT
Complement clock of low power differential CPU2/Complement clock of differential SRC pair.
The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on
powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
54
CPUT2_ITP/SRCT8
OUT
True clock of low power differential CPU2/True clock of differential SRC pair. The function of this
pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is
as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
55
NC
N/A
No Connect
56
VDDCPU_IO
PWR
1.05V to 3.3V from external power supply
57
CPUC1_F
OUT
Complement clock of low power differenatial CPU clock pair. This clock will be free-running
during iAMT.
58
CPUT1_F
OUT
True clock of low power differential CPU clock pair. This clock will be free-running during iAMT.
59
GNDCPU
PWR
Ground Pin for CPU Outputs
60
CPUC0
OUT
Complement clock of low power differential CPU clock pair.
61
CPUT0
OUT
True clock of low power differential CPU clock pair.
62
VDDCPU
PWR
Power Supply 3.3V nominal.
63
CK_PWRGD/PD#
IN
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
64
FSLB/TEST_MODE
IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for
Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N
divider mode while in test mode. Refer to Test Clarification Table.
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