参数资料
型号: A1010B-1PL68I
厂商: Microsemi SoC
文件页数: 25/98页
文件大小: 0K
描述: IC FPGA 1200 GATES 68-PLCC IND
标准包装: 19
系列: ACT™ 1
LAB/CLB数: 295
输入/输出数: 57
门数: 1200
电源电压: 4.5 V ~ 5.5 V
安装类型: 表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 68-LCC(J 形引线)
供应商设备封装: 68-PLCC(24.23x24.23)
31
Hi R e l F P GA s
A1 28 0A T i m i n g C har a c t e r i st i c s (continued)
(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25°C)
‘–1’ Speed
‘Std’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Units
Input Module Propagation Delays
tINYH
Pad to Y High
4.0
4.7
ns
tINYL
Pad to Y Low
3.6
4.3
ns
tINGH
G to Y High
6.9
8.1
ns
tINGL
G to Y Low
6.6
7.7
ns
Input Module Predicted Routing Delays1
tRD1
FO=1 Routing Delay
6.2
7.3
ns
tRD2
FO=2 Routing Delay
7.2
8.4
ns
tRD3
FO=3 Routing Delay
7.7
9.1
ns
tRD4
FO=4 Routing Delay
8.9
10.5
ns
tRD8
FO=8 Routing Delay
12.9
15.2
ns
Global Clock Network
tCKH
Input Low to High
FO = 32
FO = 384
13.3
17.9
15.7
21.1
ns
tCKL
Input High to Low
FO = 32
FO = 384
13.3
18.2
15.7
21.4
ns
tPWH
Minimum Pulse Width High
FO = 32
FO = 384
6.9
7.9
8.1
9.3
ns
tPWL
Minimum Pulse Width Low
FO = 32
FO = 384
6.9
7.9
8.1
9.3
ns
tCKSW
Maximum Skew
FO = 32
FO = 384
0.6
3.1
0.6
3.1
ns
tSUEXT
Input Latch External Setup
FO = 32
FO = 384
0.0
ns
tHEXT
Input Latch External Hold
FO = 32
FO = 384
8.6
13.8
8.6
13.8
ns
tP
Minimum Period
FO = 32
FO = 384
13.7
16.0
16.2
18.9
ns
fMAX
Maximum Frequency
FO = 32
FO = 384
73
63
62
53
MHz
Note:
1.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce delays by 0
to 4 ns.
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