参数资料
型号: A1280A-1CQG172M
元件分类: FPGA
英文描述: FPGA, 1232 CLBS, 8000 GATES, 60 MHz, CQFP172
封装: CERAMIC, CQFP-172
文件页数: 51/54页
文件大小: 333K
代理商: A1280A-1CQG172M
RadTolerant FPGAs
1- 2
v3.1
QML Certification
Actel has achieved full QML certification, demonstrating
that quality management, procedures, processes, and
controls are in place and comply with MIL-PRF-38535, the
performance specification used by the Department of
Defense
for
monolithic
integrated
circuits.
QML
certification is an example of Actel's commitment to
supplying the highest quality products for all types of
high-reliability, military and space applications.
Many suppliers of microelectronics components have
implemented QML as their primary worldwide business
system. Appropriate use of this system not only helps in
the implementation of advanced technologies, but also
allows for quality, reliable and cost-effective logistics
support throughout the QML products life cycles.
Disclaimer
All radiation performance information is provided for
information purposes only and is not guaranteed. The
total dose effects are lot-dependent, and Actel does not
guarantee that future devices will continue to exhibit
similar radiation characteristics. In addition, actual
performance can vary widely due to a variety of factors,
including but not limited to characteristics of the orbit,
radiation environment, proximity to satellite exterior,
amount of inherent shielding from other sources within
the satellite, and actual bare die variations. For these
reasons, Actel does not guarantee any level of radiation
survivability, and it is solely the responsibility of the
customer to determine whether the device will meet the
requirements of the specific design.
Development Tool Support
The HiRel devices are fully supported by both the Actel
Libero Integrated Design Environment (IDE) and
Designer FPGA Development software. Actel Libero IDE
is
a
design
management
environment,
seamlessly
integrating design tools while guiding the user through
the design flow, managing all design and log files, and
passing necessary design data among tools. Libero IDE
allows users to integrate both schematic and HDL
synthesis into a single flow and verify the entire design
in a single environment. Libero IDE includes Synplify for
Actel from Synplicity, ViewDraw for Actel from
Mentor Graphics, ModelSim HDL Simulator from
Mentor
Graphics,
WaveFormer
Lite
from
SynaptiCAD, and Designer software from Actel. Refer
to the Libero IDE flow diagram for more information.
Actel's Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
timing-driven
place-and-route,
and
a
world-class
integrated static timing analyzer and constraints editor.
With the Designer software, a user can select and lock
package pins while only minimally impacting the results of
place-and-route. Additionally, the back-annotation flow is
compatible with all the major simulators and the
simulation results can be cross-probed with Silicon Explorer
II, Actel’s integrated verification and logic analysis tool.
Another tool included in the Designer software is the
ACTgen macro builder, which easily creates popular and
commonly used logic functions for implementation into
your schematic or HDL design. Actel's Designer software is
compatible with the most popular FPGA design entry and
verification tools from companies such as Mentor Graphics,
Synplicity, Synopsys, and Cadence Design Systems. The
Designer software is available for both the Windows and
UNIX operating systems.
RadTolerant Architecture
The Actel architecture is composed of fine-grained logic
modules that produce fast, efficient logic designs. All
devices
are
composed
of
logic
modules,
routing
resources, clock networks, and I/O modules, which are
the building blocks for fast logic designs.
Logic Modules
These RadTolerant devices contain two types of logic
modules, combinatorial (C-modules) and sequential
(S-modules). RT1020 and A1020B devices contain only C-
modules.
The C-module, shown in Figure 1-1, implements EQ 1-1:
Y = !S1*!S0*D00+!S1*S0*D01+S1*!S0*D10+S1*S0*D11
EQ 1-1
where:
S0 = A0 * B0
S1 = A1+ B1
Figure 1-1 C-Module Implementation
D00
D01
D10
D11
S0
S1
Y
A0
B0
A1
B1
相关PDF资料
PDF描述
A1280A-CQG172B FPGA, 1232 CLBS, 8000 GATES, 41 MHz, CQFP172
A1280A-CQG172M FPGA, 1232 CLBS, 8000 GATES, 41 MHz, CQFP172
A1020B-CQ84C FPGA, 547 CLBS, 2000 GATES, 37 MHz, CQFP84
A14100A-1CQ256B FPGA, 1377 CLBS, 30000 GATES, 100 MHz, CQFP256
A1280A-1CQ172E FPGA, 1232 CLBS, 8000 GATES, 60 MHz, CQFP172
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