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参数资料
| 型号： | A3980KLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 12/19页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER MICROSTEPPING 28-TSSOP |
| 标准包装： | 1 |
| 应用： | 步进电机驱动器 |
| 输出数： | 1 |
| 电流 - 输出： | ± 1A |
| 电压 - 负载： | 7 V ~ 50 V |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 28-TSSOP 裸露焊盘 |
| 包装： | 标准包装 |
| 产品目录页面： | 1140 (CN2011-ZH PDF) |
| 其它名称： | 620-1298-6 |
A3980
Automotive DMOS Microstepping Driver
with Translator
as shown in table 3. In all other modes, V REF should not be
allowed to exceed 4 V, because the peak sense value can
reach V REF ? 8, or 100%.
Fixed Off-Time. The internal PWM current control
circuitry uses a one-shot circuit to control the duration of
time that the DMOS FETs remain off. The one shot off-time,
t OFF , is determined for each of the two phases by the combi-
nation of an external resistor (R T ) and a capacitor (C T ). One
combination is connected from the timing terminal RC1 to
ground, and the other similarly connected to RC2 . t OFF (ns)
is approximated by
capacitor (C CP ), capable of withstanding the battery volt-
age VBATT, should be connected between CP1 and CP2.
In addition, a 100 nF ceramic capacitor (C CS )is required
between VCP and VBB, to act as a reservoir for operating
the high-side DMOS devices. The voltage on C CS is limited to
the charge pump voltage, which is always less than 10 V.
VREG (VREG) . This internally-generated voltage is used
to operate the sink-side DMOS FETs. The VREG terminal
must be decoupled with a 220 nF (10V) capacitor to ground.
VREG is internally monitored. In the case of a fault condi-
tion, the DMOS outputs of the A3980 are disabled.
t OFF = R T
× C T
Enable Input (ENABLE) . This input simply turns off all
of the DMOS outputs. When set to a logic high, the outputs
over a range of values from C T = 470 pF to 1500 pF and from
R T = 12 k Ω to 100 k Ω .
RC Blanking. In addition to the ? xed off-time of the
PWM control circuit, the C T component sets the comparator
blanking time. This function blanks the output of the current
sense comparators when the outputs are switched by the
internal current control circuitry. The comparator outputs are
blanked to prevent false overcurrent detection due to reverse
recovery currents of the clamp diodes, and switching tran-
sients related to the capacitance of the load. The blank time,
t BLANK (ns), can be approximated by
t BLANK = 1400 × C T
where C T is the value of the capacitor C T (nF).
The blank time should be as short as possible, without caus-
ing a false fault detection, to ensure that power dissipation
during a fault condition is minimized. The blank time also
de ? nes the minimum duration of time that the full-bridge
DMOS outputs cause the load current to rise. To ensure
correct detection of motor faults, the minimum on-time is
are disabled. When set to a logic low, the internal control
enables the outputs as required. The translator inputs (STEP,
DIR, MS1, and MS2), as well as the internal sequencing
logic, all remain active, independent of the ENABLE input
state.
Sleep Mode (SLEEP). To minimize power consumption
when the motor is not in use, this input disables much of the
internal circuitry including the output DMOS FETs, voltage
regulator, and charge pump. A logic low on the SLEEP termi-
nal puts the A3980 into Sleep mode. A logic high allows nor-
mal operation, as well as start-up (at which time the A3980
drives the motor to the Home microstep position). If the
A3980 comes out of Sleep mode when V BB is greater than
V OVB – V OVBH and less than V OVB , the A3980 will remain
in safety mode until V BB is reduced below V OVB - V OVBH .
Percent Fast Decay Input (PFD) . When a STEP input
signal commands an output current level that is lower than
that of the previous step, it switches the output current decay
to slow, fast, or mixed decay mode, depending on the voltage
level at the PFD input, as shown in the following table.
extended by an additional fault sampling time, t SCT . The
minimum on-time, t MINON is then
Lower PFD Input
Voltage Level
Decay Mode
t MINON = t BLANK + t SCT
V PFD > (0.6
× V DD )
Slow
Charge Pump (CP1 and CP2). The charge pump is
used to generate a gate supply greater than that of VBB for
driving the source-side DMOS gates. A 100 nF ceramic
(0.21 × V DD ) ≤ V PFD ≤ (0.6 × V DD )
V PFD < (0.21 × V DD )
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Mixed
Fast
11
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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