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参数资料
| 型号： | A3980KLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 16/19页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER MICROSTEPPING 28-TSSOP |
| 标准包装： | 1 |
| 应用： | 步进电机驱动器 |
| 输出数： | 1 |
| 电流 - 输出： | ± 1A |
| 电压 - 负载： | 7 V ~ 50 V |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 28-TSSOP 裸露焊盘 |
| 包装： | 标准包装 |
| 产品目录页面： | 1140 (CN2011-ZH PDF) |
| 其它名称： | 620-1298-6 |
A3980
Automotive DMOS Microstepping Driver
with Translator
The total dissipation for each of the four decay modes is the
Non-synchronous slow decay mode:
average power for the current ramp and the current decay
portions of the PWM cycle.
P TOT = (0.2
× P D ) + (0.8 × P NS )
For slow decay, the current is rising for approximately 20%
of the cycle and decaying for approximately 80%. For fast
P TOT = [0.2
× I 2 (R DSONH +R DSONL )]+{0.8 × [I 2 R DSONL +(I × V F )]}
decay, the ratio is approximately 50% for each. Note that
these are approximate ? gures, and they vary slightly depend-
ing on the motor characteristics and the use of synchronous
recti ? cation.
The power dissipation, P TOT , in each decay mode can be
calculated as shown in the following formulas.
Synchronous fast decay mode:
P TOT = (0.5 × P D ) + (0.5 × P SF )
P TOT = I 2 (R DSONH + R DSONL )
Non-synchronous fast decay mode:
Synchronous slow decay mode:
P TOT = (0.2 × P D ) + (0.8 ×
P TOT = [0.2 × I 2 (R DSONH + R DSONL )] + [0.8
Allowable Package Power Dissipation
5
P SS )
× I 2 (2
× R DSONL )]
P TOT = (0.5 × P D ) + (0.5 × P NF )
P TOT = [0.5 × I 2 (R DSONH + R DSONL )] + (0.5 × I 2 × R DSONL )
An approximation of the total dissipation can be calculated
by summing the total power dissipated in both full-bridges
and adding the control circuit power due to V BB × I BB and
V DD × I DD . The total power at the required ambient tempera-
ture can then be compared to the allowable power dissipation,
shown in the Allowable Package Power Dissipation chart.
For critical applications, where the ? rst order power estimate
is close to the allowable dissipation, the power calculation
4
3
should take several other parameters into account including:
motor parameters, dead time, and switching losses in the
controller.
Layout. The printed circuit board should use a heavy
1 R
θ JA
= 28oC/W
ground plane. For optimum electrical and thermal perfor-
mance, the A3980 should be soldered directly onto the board.
2
2 R
θ JA
= 38oC/W
The load supply terminal, V BB , should be decoupled with
an electrolytic capacitor (> 47 μ F is recommended), placed
as close to the A3980 as possible. To avoid problems due to
1
capacitive coupling of the high dv/dt switching transients,
route the full-bridge output traces away from the sensitive
logic input traces. Always drive the logic inputs with a low
0
25
50
75 100
Ambient Temperature (°C)
125
150
source impedance to increase noise immunity.
Grounding. A star ground system located close to the
A3980 is recommended. On the 28-lead TSSOP package, the
1 R θ JA at 28oC/ W measured on a JEDEC-standard
“High-K” 4-layer PCB.
2 R θ JA at 38oC/ W measured on a typical 2-sided PCB
with 3 in. 2 (1935 mm 2 ) copper ground area.
analog ground (lead 7) and the power ground (lead 21) must
be connected together externally. The copper ground plane
located under the exposed thermal pad is typically used as
the star ground point.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
15
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