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参数资料
| 型号： | A3980KLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 14/19页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER MICROSTEPPING 28-TSSOP |
| 标准包装： | 1 |
| 应用： | 步进电机驱动器 |
| 输出数： | 1 |
| 电流 - 输出： | ± 1A |
| 电压 - 负载： | 7 V ~ 50 V |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 28-TSSOP 裸露焊盘 |
| 包装： | 标准包装 |
| 产品目录页面： | 1140 (CN2011-ZH PDF) |
| 其它名称： | 620-1298-6 |
A3980
Automotive DMOS Microstepping Driver
with Translator
Shorted Load. A short across the load is detected by moni-
toring the voltage across both the top and bottom FETs in each
full-bridge.
Short Fault Operation. Because motor capacitance may
cause the measured voltages to show a fault as the full-bridge
switches, voltages are not sampled until after the blank time plus
an internally-generated delay, t SCT . Once a short circuit has been
detected, all outputs for the faulty phase are disabled until the
next step command. At the next step command, the outputs are
re-enabled and the voltage across the FET is resampled.
While the fault persists, the A3980 continues this cycle at each
step command: enabling the outputs for a short period, and then
disabling the outputs. This allows the A3980 to handle a continu-
ous short circuit without damage. If, while stepping rapidly, a
short circuit appears and no action is taken, the repeated short-cir-
cuit current pulses eventually cause the temperature of the A3980
to rise and an overtemperature fault occurs.
Low Load Current Fault Operation. A low load current is
detected by monitoring the measured phase current in each output
while driving the motor in the Home microstep position. At the
Home microstep position, each phase current should reach 70%
of I TripMax . If either phase current does not exceed half of this
expected value (more than 35% of I TripMax ) while in the Home
microstep position, then a low load current condition is reported
on the next rising edge of the STEP input. If the measured cur-
rent in both phases exceeds 35% of I TripMax ) then no fault will be
generated on the next rising edge of the STEP input.
If an open load condition appears while stepping, then it is
detected after the translator cycles through the Home state.
Although the A3980 continues to drive the DMOS outputs during
an open load condition, it does not clear the fault ? ags until the
next Home state occurs.
There are two conditions that can cause a low load current. The
? rst is an open circuit on either or both motor phase connections.
In this condition, current can never ? ow through the phase so a
low load current will always be ? agged. The second condition is
where the back EMF of the motor limits the phase current to less
than the low load current trip level. This will happen when the
stepper motor is running close to its limiting speed. To con ? rm an
open load condition when a low load current is ? agged, the step
rate should be reduced to a level below half the maximum step
rate. If the low load current ? ag remains active at the lower step
rate, after completing the number of steps required to pass the
home condition, then an open circuit condition is con ? rmed.
To allow immediate detection of an open load condition at power
up or after coming out of sleep mode, the A3980 translator is
reset to the Home microstep position and the low load current
fault ? ags are set. If no open load condition exists then the fault
? ags will be reset on the next rising edge of the STEP input.
Supply Monitors. External and internal supplies are moni-
tored to ensure that they are within the correct operating range.
If the main supply exceeds the overvoltage limit, V OVB , the fault
? ags are set and the A3980 enters a safety mode in which all low-
side DMOS FETs are enabled and all high-side DMOS FETs are
disabled. This allows the A3980 to survive a load dump transient
condition that has up to 50 V on VBATT and a duration of up
to 500 ms. If the internal regulator V REG or the logic supply V DD go
below their respective undervoltage limits (V UVR or V UVD ), then: the
fault ? ags are set, the DMOS outputs are disabled, and the internal
logic is reset to the power-on state (the translator is set to the Home
state).
Diagnostic Fault Flags (FF1, FF2) . Diagnostic fault con-
ditions are reported using the two fault ? ag outputs (open drain).
These are active-low outputs which are coded as shown in table
2 to discriminate between the fault conditions. When both fault
? ags are high, no fault exists.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
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