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| 型号： | A4989SLDTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 14/17页 |
| 文件大小： | 0K |
| 描述： | IC FULL BRDG MFET DRVR 38TSSOP |
| 标准包装： | 1 |
| 应用： | 步进电机控制器，2 相 |
| 输出数： | 1 |
| 电压 - 负载： | 12 V ~ 50 V |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 38-TSSOP |
| 包装： | 标准包装 |
| 其它名称： | 620-1389-6 |
A4989
PFD1 and PFD2 The Percent Fast Decay pins are used to
select the portion of fast decay, according to table 2, to be used
when mixed decay is enabled. Mixed decay is enabled when a
Dual Full-Bridge MOSFET Driver
with Microstepping Translator
the low R DS(ON) of the MOSFET. This lowers power dissipa-
tion significantly and eliminates the need for additional Schottky
diodes. Synchronous rectification can be set to either active mode
STEP input signal commands an output current that is lower than
for the previous step. In mixed decay mode, as the trip point is
reached, the A4989 goes into fast decay mode until the specified
number of master oscillator cycles has completed. After this fast
decay portion, the A4989 switches to slow decay mode for the
remainder of the fixed off-time, t OFF .
Using PFD1 and PFD 2 to select 0% fast decay will effectively
maintain the full-bridge in slow decay at all times. This option
can be used to keep the phase current ripple to a minimum when
the motor is stationary or stepping at very low rates.
Selecting 100% fast decay will provide the fastest current control
when the current is falling and can help when the motor is being
driven at very high step rates.
SR Input used to set synchronous rectification mode. When a
PWM off-cycle is triggered, load current recirculates according
to the decay mode selected by the control logic. The synchronous
rectification feature turns on the appropriate MOSFETs during
the current decay and effectively shorts out the body diodes with
or disabled mode.
? Active Mode When the SR pin input is logic low, active mode
is enabled and synchronous rectification will occur. This mode
prevents reversal of the load current by turning off synchro-
nous rectification when a zero current level is detected. This
prevents the motor winding from conducting in the reverse
direction.
? Disabled Mode When the SR pin input is logic high, synchro-
nous rectification is disabled. This mode is typically used when
external diodes are required to transfer power dissipation from
the power MOSFETs to external, usually Schottky, diodes.
Shutdown Operation In the event of an overtemperature
fault, or an undervoltage fault on VREG, the MOSFETs are
disabled until the fault condition is removed. At power-up, and
in the event of low voltage at VDD, the under voltage lockout
(UVLO) circuit disables the MOSFETs until the voltage at VDD
reaches the minimum level. Once V DD is above the minimum
level, the translator is reset to the home state, and the MOSFETs
are reenabled.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
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