- 您现在的位置：买卖IC网 > PDF目录1774 > A4989SLDTR-T (Allegro Microsystems Inc)IC FULL BRDG MFET DRVR 38TSSOP PDF资料下载
参数资料
| 型号： | A4989SLDTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 15/17页 |
| 文件大小： | 0K |
| 描述： | IC FULL BRDG MFET DRVR 38TSSOP |
| 标准包装： | 1 |
| 应用： | 步进电机控制器，2 相 |
| 输出数： | 1 |
| 电压 - 负载： | 12 V ~ 50 V |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 38-TSSOP |
| 包装： | 标准包装 |
| 其它名称： | 620-1389-6 |
A4989
Dual Full-Bridge MOSFET Driver
with Microstepping Translator
Application Information
Current Sensing
To minimize inaccuracies in sensing the I PEAK current
level caused by ground-trace IR drops, the sense resistor,
RSENSE x , should have an independent return to the supply
ground star point. For low-value sense resistors, the IR drops
in the sense resistor PCB traces can be significant and should
be taken into account. The use of sockets should be avoided
as they can introduce variation in R SENSE x due to their con-
tact resistance.
Thermal Protection
All drivers are turned off when the junction temperature
reaches 165°C typical. This is intended only to protect the
A4989 from failures due to excessive junction temperatures.
Thermal protection will not protect the A4989 from continu-
ous short circuits. Thermal shutdown has a hysteresis of
approximately 15°C.
Circuit Layout
Because this is a switch-mode application, where rapid cur-
rent changes are present, care must be taken during layout of
the application PCB. The following points are provided as
guidance for layout. Following all guidelines will not always
be possible. However, each point should be carefully consid-
ered as part of any layout procedure.
Ground connection layout recommendations:
1. Decoupling capacitors for the supply pins VBB, VREG,
and VDD should be connected independently close to the
GND pin and not to any ground plane. The decoupling
capacitors should also be connected as close as possible to
the corresponding supply pin.
2. The oscillator timing resistor ROSC should be connected
to the GND pin. It should not be connected to any ground
plane, supply common, or the power ground.
3. The GND pin should be connected by an independent low
impedance trace to the supply common at a single point.
4. Check the peak voltage excursion of the transients on
the LSS pin with reference to the GND pin using a close
grounded (tip and barrel) probe. If the voltage at LSS
exceeds the absolute maximum specified in this datasheet,
add additional clamping, capacitance, or both between the
LSS pin and the AGND pin.
Other layout recommendations:
1. Gate charge drive paths and gate discharge return paths
may carry transient current pulses. Therefore, the traces from
GH xx , GL xx , S xx , and LSS x should be as short as possible to
reduce the inductance of the circuit trace.
2. Provide an independent connection from each LSS pin
to the common point of each power bridge. It is not recom-
mended to connect LSS directly to the GND pin. The LSS
connection should not be used for the SENSE connection.
3. Minimize stray inductance by using short, wide copper
runs at the drain and source terminals of all power FETs.
This includes motor lead connections, the input power bus,
and the common source of the low-side power FETs. This
will minimize voltages induced by fast switching of large
load currents.
4. Consider the use of small (100 nF) ceramic decoupling
capacitors across the source and drain of the power FETs to
limit fast transient voltage spikes caused by trace inductance.
The above are only recommendations. Each application is
different and may encounter different sensitivities. Each
design should be tested at the maximum current, to ensure
any parasitic effects are eliminated.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
15
相关PDF资料 |
PDF描述 |
|---|---|
| A6595KA-T | IC PWR DRIVER 8BIT SER 20-DIP |
| A6B259KLWTR | IC PWR DRVR 8BIT ADDRESS 20SOIC |
| A6B273KLWTR | IC PWR DRVR 8BIT ADDRESS 20SOIC |
| A8287SLBTR | IC REG LNB SUPPLY/CTRL 24-SOIC |
| A8290SETTR-T | IC VOLTAGE REG SGL LNB 28-QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A4990KLPTR-T | 制造商:Allegro MicroSystems LLC 功能描述:IC DVR FULL BRIDGE DUAL 20TSSOP 制造商:ALLEGRO 功能描述:AUTOMOTIVE DUAL FULL BRIDGE DR 制造商:Allegro MicroSystems LLC 功能描述:AUTOMOTIVE DUAL FULL BRIDGE DR |
| A4992KLPTR-T | 制造商:Allegro MicroSystems LLC 功能描述:AUTOMOTIVE STEPPER MOTOR DRIVE |
| A4993KLPTR-T | 功能描述:IC MOTOR DVR STEP AUTO 制造商:allegro microsystems, llc 系列:* 零件状态:有效 标准包装:4,000 |
| A4994KLPTR-T | 功能描述:IC DVR FULL BRIDGE DUAL 20TSSOP 制造商:allegro microsystems, llc 系列:* 零件状态:在售 标准包装:4,000 |
| A49FL004 | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:4 Mbit CMOS 3.3Volt-only Firmware Hub/LPC Flash Memory |
发布紧急采购，3分钟左右您将得到回复。