- 您现在的位置：买卖IC网 > PDF目录379534 > A54SX08P-TQ208 (Electronic Theatre Controls, Inc.) LM1881 Video Sync Separator; Package: MDIP; No of Pins: 8; Qty per Container: 40; Container: Rail PDF资料下载
参数资料
| 型号： | A54SX08P-TQ208 |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LM1881 Video Sync Separator; Package: MDIP; No of Pins: 8; Qty per Container: 40; Container: Rail |
| 中文描述： | 54SX家庭的FPGA |
| 文件页数： | 34/57页 |
| 文件大小： | 415K |
| 代理商： | A54SX08P-TQ208 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页当前第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页
5 4 S X F a m ily F P G A s
34
v3.1
P in De s c ript ion
C L K A /B
These pins are 3.3V/5.0V PCI/TTL clock inputs for clock
distribution networks. The clock input is buffered prior to
clocking the R-cells. If not used, this pin must be set LOW or
HIGH on the board. It must not be left floating. (For
A54SX72A, these clocks can be configured as bidirectional.)
C loc k A a nd B
G ND
LOW supply voltage.
G round
H C L K
De dic a te d (H a rd-w ire d)
A rra y C loc k
This pin is the 3.3V/5.0V PCI/TTL clock input for sequential
modules. This input is directly wired to each R-cell and
offers clock speeds independent of the number of R-cells
being driven. If not used, this pin must be set LOW or HIGH
on the board. It must not be left floating.
I/O
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations, input
and output levels are compatible with standard TTL, LVTTL,
3.3V PCI or 5.0V PCI specifications. Unused I/O pins are
automatically tristated by the Designer Series software.
Input/Output
NC
This pin is not connected to circuitry within the device.
No C onne c tion
P R A , I/O
The Probe A pin is used to output data from any
user-defined design node within the device. This
independent diagnostic pin can be used in conjunction with
the Probe B pin to allow real-time diagnostic output of any
signal path within the device. The Probe A pin can be used
as a user-defined I/O when verification has been completed.
The pin’s probe capabilities can be permanently disabled to
protect programmed design confidentiality.
P robe A
P R B , I/O
The Probe B pin is used to output data from any node within
the device. This diagnostic pin can be used in conjunction
with the Probe A pin to allow real-time diagnostic output of
any signal path within the device. The Probe B pin can be
used as a user-defined I/O when verification has been
completed. The pin’s probe capabilities can be permanently
disabled to protect programmed design confidentiality.
P robe B
T C K
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active when
the TMS pin is set LOW (refer to
Table2 on page8
). This pin
functions as an I/O when the boundary scan state machine
reaches the “logic reset” state.
Te s t C loc k
T DI
Serial input for boundary scan testing and diagnostic probe.
In flexible mode, TDI is active when the TMS pin is set LOW
(refer to
Table 2 on page 8
). This pin functions as an I/O
when the boundary scan state machine reaches the “logic
reset” state.
Te s t Da ta Input
T DO
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set LOW (refer to
Table 2
on page 8
). This pin functions as an I/O when the boundary
scan state machine reaches the “logic reset” state.
Te s t Da ta Output
T MS
The TMS pin controls the use of the IEEE 1149.1 Boundary
Scan pins (TCK, TDI, TDO). In flexible mode when the TMS
pin is set LOW, the TCK, TDI, and TDO pins are boundary
scan pins (refer to
Table 2 on page 8
). Once the boundary
scan pins are in test mode, they will remain in that mode
until the internal boundary scan state machine reaches the
“logic reset” state. At this point, the boundary scan pins will
be released and will function as regular I/O pins. The “logic
reset” state is reached 5 TCK cycles after the TMS pin is set
HIGH. In dedicated test mode, TMS functions as specified in
the IEEE 1149.1 specifications.
Te s t Mode S e le c t
V
C C I
Supply voltage for I/Os. See
Table 1 on page 8
.
S upply V olta g e
V
C C A
Supply voltage for Array. See
Table 1 on page 8
.
S upply V olta g e
V
C C R
Supply voltage for input tolerance (required for internal
biasing) See
Table 1 on page 8
.
S upply V olta g e
相关PDF资料 |
PDF描述 |
|---|---|
| A54SX08P-TQ208I | LM1894 Dynamic Noise Reduction System DNR®; Package: SOIC NARROW; No of Pins: 14; Qty per Container: 55; Container: Rail |
| A54SX08P-TQ208M | 54SX Family FPGAs |
| A54SX08P-TQ208PP | 54SX Family FPGAs |
| A54SX16-2FG208M | 54SX Family FPGAs |
| A54SX16-2FG208PP | 54SX Family FPGAs |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A54SX08P-TQ208I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:54SX Family FPGAs |
| A54SX08P-TQ208M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:54SX Family FPGAs |
| A54SX08P-TQ208PP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:54SX Family FPGAs |
| A54SX08P-VQ208 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:54SX Family FPGAs |
| A54SX08P-VQ208I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:54SX Family FPGAs |
发布紧急采购，3分钟左右您将得到回复。