参数资料
| 型号： | A54SX16-CQ208B |
| 厂商： | Microsemi SoC |
| 文件页数： | 31/64页 |
| 文件大小： | 0K |
| 描述： | IC FPGA SX 24K GATES 208-CQFP |
| 标准包装： | 1 |
| 系列： | SX |
| LAB/CLB数： | 1452 |
| 输入/输出数： | 175 |
| 门数： | 24000 |
| 电源电压： | 3 V ~ 3.6 V，4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 208-BFCQFP，带拉杆 |
| 供应商设备封装： | 208-CQFP（75x75） |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页当前第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页
SX Family FPGAs
v3.2
1-33
Pin Description
CLKA/B
Clock A and B
These pins are 3.3 V / 5.0 V PCI/TTL clock inputs for clock
distribution networks. The clock input is buffered prior
to clocking the R-cells. If not used, this pin must be set
LOW or HIGH on the board. It must not be left floating.
(For A54SX72A, these clocks can be configured as
bidirectional.)
GND
Ground
LOW supply voltage.
HCLK
Dedicated (hardwired) Array Clock
This pin is the 3.3 V / 5.0 V PCI/TTL clock input for sequential
modules. This input is directly wired to each R-cell and
offers clock speeds independent of the number of R-cells
being driven. If not used, this pin must be set LOW or
HIGH on the board. It must not be left floating.
I/O
Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations,
input and output levels are compatible with standard
TTL, LVTTL, 3.3 V PCI or 5.0 V PCI specifications. Unused
I/O pins are automatically tristated by the Designer Series
software.
NC
No Connection
This pin is not connected to circuitry within the device.
PRA, I/O
Probe A
The Probe A pin is used to output data from any user-
defined design node within the device. This independent
diagnostic pin can be used in conjunction with the Probe
B pin to allow real-time diagnostic output of any signal
path within the device. The Probe A pin can be used as a
user-defined I/O when verification has been completed.
The pin’s probe capabilities can be permanently disabled
to protect programmed design confidentiality.
PRB, I/O
Probe B
The Probe B pin is used to output data from any node
within the device. This diagnostic pin can be used in
conjunction with the Probe A pin to allow real-time
diagnostic output of any signal path within the device.
The Probe B pin can be used as a user-defined I/O when
verification has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality.
TCK
Test Clock
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active
when the TMS pin is set LOW (refer to Table 1-2 on
page 1-6). This pin functions as an I/O when the
boundary scan state machine reaches the "logic reset"
state.
TDI
Test Data Input
Serial input for boundary scan testing and diagnostic
probe. In flexible mode, TDI is active when the TMS pin is
set LOW (refer to Table 1-2 on page 1-6). This pin
functions as an I/O when the boundary scan state
machine reaches the "logic reset" state.
TDO
Test Data Output
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set LOW (refer to
Table 1-2 on page 1-6). This pin functions as an I/O when
the boundary scan state machine reaches the “logic
reset” state.
TMS
Test Mode Select
The TMS pin controls the use of the IEEE 1149.1
Boundary Scan pins (TCK, TDI, TDO). In flexible mode
when the TMS pin is set LOW, the TCK, TDI, and TDO pins
are boundary scan pins (refer to Table 1-2 on page 1-6).
Once the boundary scan pins are in test mode, they will
remain in that mode until the internal boundary scan
state machine reaches the "logic reset" state. At this
point, the boundary scan pins will be released and will
function as regular I/O pins. The "logic reset" state is
reached 5 TCK cycles after the TMS pin is set HIGH. In
dedicated test mode, TMS functions as specified in the
IEEE 1149.1 specifications.
VCCI
Supply Voltage
Supply voltage for I/Os. See Table 1-1 on page 1-5.
VCCA
Supply Voltage
Supply voltage for Array. See Table 1-1 on page 1-5.
VCCR
Supply Voltage
Supply voltage for input tolerance (required for internal
biasing). See Table 1-1 on page 1-5.
相关PDF资料 |
PDF描述 |
|---|---|
| EP4SGX110DF29C4 | IC STRATIX IV FPGA 110K 780FBGA |
| 93C56A-I/MS | IC EEPROM 2KBIT 2MHZ 8MSOP |
| EP1S60F1020C6N | IC STRATIX FPGA 60K LE 1020-FBGA |
| A54SX32A-1CQ256 | IC FPGA SX 48K GATES 256-CQFP |
| 93C56A-I/ST | IC EEPROM 2KBIT 2MHZ 8TSSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A54SX16-CQ208M | 功能描述:IC FPGA SX 24K GATES 208-CQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:SX 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP，带拉杆 供应商设备封装:352-CQFP（75x75） |
| A54SX16-CQ256 | 功能描述:IC FPGA SX 24K GATES 256-CQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:SX 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP，带拉杆 供应商设备封装:352-CQFP（75x75） |
| A54SX16-CQ256B | 功能描述:IC FPGA SX 24K GATES 256-CQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:SX 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP，带拉杆 供应商设备封装:352-CQFP（75x75） |
| A54SX16P-1PQ208 | 功能描述:IC FPGA SX 24K GATES 208-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:SX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A54SX16P-1PQ208I | 功能描述:IC FPGA SX 24K GATES 208-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:SX 产品培训模块:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色产品:Cyclone? IV FPGAs 标准包装:60 系列:CYCLONE® IV GX LAB/CLB数:9360 逻辑元件/单元数:149760 RAM 位总计:6635520 输入/输出数:270 门数:- 电源电压:1.16 V ~ 1.24 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:484-BGA 供应商设备封装:484-FBGA（23x23） |
发布紧急采购，3分钟左右您将得到回复。