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参数资料
| 型号： | A80960HT60 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
| 中文描述： | 32-BIT, 60 MHz, RISC PROCESSOR, CPGA168 |
| 封装： | CERAMIC, PGA-168 |
| 文件页数： | 19/78页 |
| 文件大小： | 835K |
| 代理商： | A80960HT60 |
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Advance Information Datasheet
19
80960JA/JF/JD/JT 3.3 V Microprocessor
BLAST
O
R(1)
H(Z)
P(1)
BURST LAST
indicates the last transfer in a bus access. BLAST is asserted in the
last data transfer of burst and non-burst accesses. BLAST remains active as long as
wait states are inserted via the RDYRCV pin. BLAST becomes inactive after the final
data transfer in a bus cycle.
0 = last data transfer
1 = not last data transfer
RDYRCV
I
S(L)
READY/RECOVER
indicates that data on AD lines can be sampled or removed. If
RDYRCV is not asserted during a T
d
cycle, the T
d
cycle is extended to the next cycle
by inserting a wait state (T
w
).
0 = sample data
1 = don’t sample data
The RDYRCV pin has another function during the recovery (T
r
) state. The processor
continues to insert additional recovery states until it samples the pin HIGH. This
function gives slow external devices more time to float their buffers before the
processor begins to drive address again.
0 = insert wait states
1 = recovery complete
LOCK/
ONCE
I/O
S(L)
R(H)
H(Z)
P(1)
BUS LOCK
indicates that an atomic read-modify-write operation is in progress. The
LOCK output is asserted in the first clock of an atomic operation and deasserted in
the last data transfer of the sequence. The processor does not grant HOLDA while it
is asserting LOCK. This prevents external agents from accessing memory involved
in semaphore operations.
0 = Atomic read-modify-write in progress
1 = Atomic read-modify-write not in progress
ONCE MODE:
The processor samples the ONCE input during reset. If it is asserted
LOW at the end of reset, the processor enters ONCE mode. In ONCE mode, the
processor stops all clocks and floats all output pins. The pin has a weak internal
pullup which is active during reset to ensure normal operation when the pin is left
unconnected.
0 = ONCE mode enabled
1 = ONCE mode not enabled
HOLD
I
S(L)
HOLD
: A request from an external bus master to acquire the bus. When the
processor receives HOLD and grants bus control to another master, it asserts
HOLDA, floats the address/data and control lines and enters the T
h
state. When
HOLD is deasserted, the processor deasserts HOLDA and enters either the T
i
or
T
a
state, resuming control of the address/data and control lines.
0 = no hold request
1 = hold request
HOLDA
O
R(Q)
H(1)
P(Q)
HOLD ACKNOWLEDGE
indicates to an external bus master that the processor has
relinquished control of the bus. The processor can grant HOLD requests and enter
the T
h
state during reset and while halted as well as during regular operation.
0 = hold not acknowledged
1 = hold acknowledged
BSTAT
O
R(0)
H(Q)
P(0)
BUS STATUS
indicates that the processor may soon stall unless it has sufficient
access to the bus; see
i960
Jx Microprocessor Developer’s Manual
(272483).
Arbitration logic can examine this signal to determine when an external bus master
should acquire/relinquish the bus.
0 = no potential stall
1 = potential stall
Table 3.
Pin Description — External Bus Signals (Sheet 3 of 3)
NAME
TYPE
DESCRIPTION
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|---|---|
| A80960JF-16 | EMBEDDED 32-BIT MICROPROCESSOR |
| A80960JF-25 | EMBEDDED 32-BIT MICROPROCESSOR |
| A80960JT-75 | EMBEDDED 32-BIT MICROPROCESSOR |
| A80960JT-100 | EMBEDDED 32-BIT MICROPROCESSOR |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| A80960HT75 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| A80960HT75 S L2GP | 制造商:Intel 功能描述:MPU i960 制造商:Intel 功能描述:MPU i960? Processor RISC 32-Bit 75MHz 168-Pin CPGA |
| A80960HT75S L2GP | 制造商:Intel 功能描述: |
| A80960HT75SL2GP | 功能描述:IC MPU I960HT 3V 75MHZ 168-PGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:- 标准包装:40 系列:MPC83xx 处理器类型:32-位 MPC83xx PowerQUICC II Pro 特点:- 速度:267MHz 电压:0.95 V ~ 1.05 V 安装类型:表面贴装 封装/外壳:516-BBGA 裸露焊盘 供应商设备封装:516-PBGAPGE（27x27） 包装:托盘 |
| A80960JA-16 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR |
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