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参数资料
| 型号： | A8292SETTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 10/20页 |
| 文件大小： | 0K |
| 描述： | IC REG LNB SUPPLY/CONTROL 28-MLP |
| 标准包装： | 1 |
| 应用： | 转换器，模拟和数字式卫星信号接收器 |
| 输入电压： | 8 V ~ 16 V |
| 输出数： | 2 |
| 输出电压： | 12.7 V ~ 20.4 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VFQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN/MLP 裸露焊盘（5x5） |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1187-6 |
A8292
3. Data Cycles.
Dual LNB Supply and Control Voltage Regulator
the Read/Write bit is low, the master writes data to one of the four
Write – 6 bits of data and 2 bits for addressing four internal
control registers, followed by an acknowledge bit. See Control
Register section for more information.
Read – Two status registers, where register 1 is read first,
followed by register 2, then register 1, and so on. At the start
of any read sequence, register 1 is always read first. Data is
transmitted MSB first.
4. Stop Condition. Defined by a positive edge on the SDA line,
while SCL is high. Except to indicate a Start or Stop condi-
tion, SDA must be stable while the clock is high. SDA can
only be changed while SCL is low. It is possible for the Start or
Stop condition to occur at any time during a data transfer. The
A8292 always responds by resetting the data transfer sequence.
The Read/Write bit is used to determine the data transfer direc-
tion. If the Read/Write bit is high, the master reads the contents of
register 1, followed by register 2 if a further read is performed. If
Control registers. Note that multiple writes are not permitted. All
write operations must be preceded with the address.
The Acknowledge bit has two functions. It is used by the master
to determine if the slave device is responding to its address and
data, and it is used by the slave when the master is reading data
back from the slave. When the A8292 decodes the 7-bit address
field as a valid address, it responds by pulling SDA low during the
ninth clock cycle.
During a data write from the master, the A8292 also pulls SDA
low during the clock cycle that follows the data byte, in order to
indicate that the data has been successfully received. In both cases,
the master device must release the SDA line before the ninth clock
cycle, in order to allow this handshaking to occur.
acknowledge
from LNBR
acknowledge
from LNBR
Start
Address
W
Control Data
Stop
SDA
0
0
0
1
0
A1
A0
0
AK
I1
I0
D5
D4
D3
D2
D1
D0
AK
SCL
1
2
3
4
5
6
7
8
9
Write to Register
acknowledge
from LNBR
no acknowledge
from master
Start
Address
R
Status Register 1
Stop
SDA
0
0
0
1
0
A1
A0
1
AK
D7
D6
D5
D4
D3
D2
D1
D0 NAK
SCL
1
2
3
4
5
6
7
8
9
Read One Byte from Register
acknowledge
from LNBR
acknowledge
from LNBR
no acknowledge
from master
Start
Address
R
Status Data in Register 1
Status Data in Register 2
Stop
SDA
0
0
0
1
0
A1
A0
1
AK
D7
D6
D5
D4
D3
D2
D1
D0
AK
-
-
-
-
D3
D2
D1
D0 NAK
SCL
1
2
3
4
5
6
7
8
9
Read Multiple Bytes from Register
Figure 3. I 2 C? Interface. Read and write sequences.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
10
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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