参数资料
型号: A8293SETTR-T
厂商: Allegro Microsystems Inc
文件页数: 1/19页
文件大小: 0K
描述: IC REG LNB BOOST/LINEAR 28QFN
标准包装: 9,000
应用: 转换器,模拟和数字式卫星信号 STB 接收器/SatTV
输入电压: 9 V ~ 16 V
输出数: 1
输出电压: 可调
工作温度: -20°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-VFQFN
供应商设备封装: 28-QFN
包装: 带卷 (TR)
A8293
Single LNB Supply and Control Voltage Regulator
Features and Benefits
? 2-wire serial I 2 C? -compatible interface: control (write) and
status (read)
? LNB voltages (8 programmable levels) compatible with
all common standards including domestic Japan models
? Tracking switch-mode power converter for lowest dissipation
? Integrated converter switches and current sensing
? Provides up to 700 mA load current
? Static current limit circuit allows full current at startup and
13 → 18 V output transition; reliably starts wide load range
? Push-pull output stage minimizes 13 → 18 V and 18 → 13 V
output transition times for highly capacitive loads
? Adjustable rise/fall time via external timing capacitor
? Built-in tone oscillator, factory-trimmed to 22 kHz
facilitates DiSEqC? tone encoding, even at no-load
? Four methods of 22 kHz tone generation, via I 2 C? data
bits and/or external pin
? Auxiliary modulation input
? LNB overcurrent with timer
? Diagnostics for output voltage level, input supply UVLO
Packages:
20-contact, 4 × 4 mm
MLP/QFN (suffix ES)
28 contact, 5 × 5 mm
MLP/QFN (suffix ET)
Description
Intended for analog and digital satellite receivers, this single
low noise block converter regulator (LNBR) is a monolithic
linear and switching voltage regulator, specifically designed to
provide the power and the interface signals to an LNB down
converter via coaxial cable. The A8293 requires few external
components, with the boost switch and compensation circuitry
integrated inside of the device. A high switching frequency is
chosen to minimize the size of the passive filtering components,
further assisting in cost reduction. The high levels of component
integration ensure extremely low noise and ripple figures.
The A8293 has been designed for high efficiency, utilizing
the Allegro ? advanced BCD process. The integrated boost
switch has been optimized to minimize both switching and
static losses. To further enhance efficiency, the voltage drop
across the tracking regulator has been minimized.
For DiSEqC? communications, several schemes are available
for generating tone signals, all the way down to no-load, and
using either the internal clock or an external time source.
Continued on the next page…
Functional Block Diagram
L1
V S
33 μ H
D1
C1
100 nF
C2
100 μ F
VIN
LX
C5
100 μ F
GNDLX
C6
1 μ F
BOOST VCP
C4
100 nF
VREG
C3
220 nF
Regulator
Boost
Converter
TMode
Charge
Pump
D3
A
V DD
fsw
EXTM
R1 R2 R3 R4
DAC
LNB
Voltage
Control
Wave
Shape
Linear
Stage
LNB
V OUT
EXTM
TCAP
fsw
TGate
D2
C8
100 nF
C10
220 nF
C9
10 nF
D4
A
SDA
SCL
I 2 C?-
Compatible
Interface
Fault Monitor
OCP
PNG
TSD
VUV
Oscillator
Clock
Divider 22 kHz
TCAP
C7
10 nF (or 22 nF)
ADD
IRQ
PAD
GND
A
D3 and D4 are used for surge protection.
For recommended external components, refer to table 7
8293-DS, Rev. 4
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