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参数资料
| 型号： | A8293SETTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 14/19页 |
| 文件大小： | 0K |
| 描述： | IC REG LNB BOOST/LINEAR 28QFN |
| 标准包装： | 9,000 |
| 应用： | 转换器，模拟和数字式卫星信号 STB 接收器/SatTV |
| 输入电压： | 9 V ~ 16 V |
| 输出数： | 1 |
| 输出电压： | 可调 |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VFQFN |
| 供应商设备封装： | 28-QFN |
| 包装： | 带卷 (TR) |
A8293
Single LNB Supply and Control Voltage Regulator
Table 5. Status Register 1
Bit
0
1
2
3
4
5
6
7
Name
DIS
–
OCP
–
PNG
–
TSD
VUV
Function
LNB output disabled
Not Used
Overcurrent
Not Used
Power Not Good
Not Used
Thermal Shutdown
V IN Undervoltage
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
DIS
–
OCP
–
PNG
–
TSD
VUV
LNB Output Disabled. DIS is used to indicate the current condition of the LNB
output. At power-on, or if a fault condition occurs, DIS will be set. This bit changing
to 1 does not cause the IRQ to activate because the LNB output may be disabled in-
tentionally by the I 2 C? master. This bit will be reset at the end of a write sequence
if the LNB output is enabled.
Not used.
Overcurrent. If the LNB output detects an overcurrent condition, for greater than
48 ms, the LNB output will be disabled. The OCP bit will be set to indicate that an
overcurrent has occurred and the disable bit, DIS, will be set. The Status register is
updated on the rising edge of the 9 th clock pulse in the data read sequence, where the
OCP bit is reset in all cases, allowing the master to reenable the LNB output.
If the overcurrent timer is not enabled, the device operate in current limit indefinitely
and the OCP bit will be set. If the overcurrent condition is removed, the OCP bit will
automatically be reset. Note that if the overcurrent operates long enough, and a ther-
mal shutdown occurs, the LNB output will be disabled and the TSD bit will be set.
Not used.
Power Not Good. Set to 1 when the LNB output is enabled and the LNB voltage is
below 85% of the programmed voltage. The PNG is reset when the LNB volts are
within 90% of the programmed LNB voltage.
Not used.
Thermal Shutdown. 1 indicates that the A8293 has detected an overtemperature
condition and has disabled the LNB output. The disable bit, DIS, will also be set.
The status of the overtemperature condition is sampled on the rising edge of the 9 th
clock pulse in the data read sequence. If the condition is no longer present, then the
TSD bit will be reset, allowing the master to reenable the LNB output if required. If
the condition is still present, then the TSD bit will remain at 1.
Undervoltage Lockout. 1 indicates that the A8293 has detected that the input sup-
ply, V IN is, or has been, below the minimum level and an undervoltage lockout has
occurred disabling the LNB outputs. The disable bit, DIS, will also be set and the
A8293 will not reenable the output until so instructed by writing the relevant bit into
the control registers. The status of the undervoltage condition is sampled on the rising
edge of the 9 th clock pulse in the data read sequence. If the condition is no longer
present, then the VUV bit will be reset allowing the master to reenable the LNB out-
put if required. If the condition is still present, then the VUV bit will remain at 1.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
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