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| 型号： | A8293SETTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 5/19页 |
| 文件大小： | 0K |
| 描述： | IC REG LNB BOOST/LINEAR 28QFN |
| 标准包装： | 9,000 |
| 应用： | 转换器，模拟和数字式卫星信号 STB 接收器/SatTV |
| 输入电压： | 9 V ~ 16 V |
| 输出数： | 1 |
| 输出电压： | 可调 |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VFQFN |
| 供应商设备封装： | 28-QFN |
| 包装： | 带卷 (TR) |
A8293
Single LNB Supply and Control Voltage Regulator
ELECTRICAL CHARACTERISTICS (continued) at T A = 25°C, V IN = 9 to 16 V, unless noted otherwise 1
Characteristics
Tone Duty Cycle
Tone Rise Time
Tone Fall Time
EXTM Logic Input
EXTM Input Leakage
Symbol
DC TONE
t rTONE
t fTONE
V EXTM(H)
V EXTM(L)
I EXTMLKG
Test Conditions
I LOAD = 0 to 450 mA, C LOAD = 750 nF
I LOAD = 0 to 450 mA, C LOAD = 750 nF
I LOAD = 0 to 450 mA, C LOAD = 750 nF
Min.
40
5
5
2.0
–
–1
Typ.
50
10
10
–
–
–
Max.
60
15
15
–
0.8
1
Units
%
μ s
μ s
V
V
μ A
I 2 C?-Compatible Interface
Logic Input (SDA,SCL) Low Level
Logic Input (SDA,SCL) High Level
Logic Input Hysteresis
V SCL(L)
V SCL(H)
V I2CIHYS
–
2.0
–
–
–
150
0.8
–
–
V
V
mV
Logic Input Current
Logic Output Voltage SDA and IRQ
Logic Output Leakage SDA and IRQ
SCL Clock Frequency
Output Fall Time
Bus Free Time Between Stop/Start
Hold Time Start Condition
Setup Time for Start Condition
SCL Low Time
SCL High Time
Data Setup Time
Data Hold Time
I I2CI
V t2COut(L)
V t2CLKG
f CLK
t fI2COut
t BUF
t HD:STA
t SU:STA
t LOW
t HIGH
t SU:DAT
t HD:DAT
V I2CI = 0 to 7 V
I LOAD = 3 mA
V t2COut = 0 to 7 V
V t2COut(H) to V t2COut(L)
For t HD:DAT (min) , the master device must
provide a hold time of at least 300 ns for the
SDA signal in order to bridge the undefined
–10
–
–
–
–
1.3
0.6
0.6
1.3
0.6
100
0
<±1.0
–
–
–
–
–
–
–
–
–
–
–
10
0.4
10
400
250
–
–
–
–
–
–
900
μ A
V
μ A
kHz
ns
μ s
μ s
μ s
μ s
μ s
ns
ns
region of the SCL signal falling edge
Setup Time for Stop Condition
t SU:STO
0.6
–
–
μ s
I 2 C? Address Setting
ADD Voltage for Address 0001,000
ADD Voltage for Address 0001,001
ADD Voltage for Address 0001,010
ADD Voltage for Address 0001,011
Address1
Address2
Address3
Address4
0
1.3
2.3
3.3
–
–
–
–
0.7
1.7
2.7
5.0
V
V
V
V
1 Operation
at 16 V may be limited by power loss in the linear regulator.
2 Guaranteed by worst case process simulations and system characterization. Not production tested.
3 LNB output ripple and noise are dependent on component selection and PCB layout. Refer to the Application Schematic and PCB layout
recommendations. Not production tested.
4 Current from the LNB output may be limited by the choice of Boost components.
I 2 C? Interface Timing Diagram
t SU:STA
t HD:STA
t SU:DAT
t HD:DAT
t SU:STO
t BUF
SDA
SCL
t LOW
t HIGH
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
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