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参数资料
| 型号： | A8293SETTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 8/19页 |
| 文件大小： | 0K |
| 描述： | IC REG LNB BOOST/LINEAR 28QFN |
| 标准包装： | 9,000 |
| 应用： | 转换器，模拟和数字式卫星信号 STB 接收器/SatTV |
| 输入电压： | 9 V ~ 16 V |
| 输出数： | 1 |
| 输出电压： | 可调 |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VFQFN |
| 供应商设备封装： | 28-QFN |
| 包装： | 带卷 (TR) |
A8293
I 2 C?-Compatible Interface
Single LNB Supply and Control Voltage Regulator
fined by the remaining two bits, are selected by the ADD input.
The address is transmitted MSB first.
This is a serial interface that uses two bus lines, SCL and SDA,
to access the internal Control and Status registers of the A8293.
Data is exchanged between a microcontroller (master) and the
A8293 (slave). The clock input to SCL is generated by the master,
while SDA functions as either an input or an open drain output,
depending on the direction of the data.
Timing Considerations
The control sequence of the communication through the I 2 C?-
compatible interface is composed of several steps in sequence:
1. Start Condition. Defined by a negative edge on the SDA line,
while SCL is high.
2. Address Cycle. 7 bits of address, plus 1 bit to indicate read (1)
or write (0), and an acknowledge bit. The first five bits of the
address are fixed as: 00010. The four optional addresses, de-
3. Data Cycles.
Write – 6 bits of data and 2 bits for addressing four internal
control registers, followed by an acknowledge bit. See Control
Register section for more information.
Read – Two status registers, where register 1 is read first,
followed by register 2, then register 1, and so on. At the start
of any read sequence, register 1 is always read first. Data is
transmitted MSB first.
4. Stop Condition. Defined by a positive edge on the SDA line,
while SCL is high. Except to indicate a Start or Stop condi-
tion, SDA must be stable while the clock is high. SDA can
only be changed while SCL is low. It is possible for the Start or
Stop condition to occur at any time during a data transfer. The
A8293 always responds by resetting the data transfer sequence.
The Read/Write bit is used to determine the data transfer direc-
tion. If the Read/Write bit is high, the master reads the contents of
acknowledge
from LNBR
acknowledge
from LNBR
Start
Address
W
Control Data
Stop
SDA
0
0
0
1
0
A1
A0
0
AK
I1
I0
D5
D4
D3
D2
D1
D0
AK
SCL
1
2
3
4
5
6
7
8
9
Write to Register
acknowledge
from LNBR
no acknowledge
from master
Start
Address
R
Status Register 1
Stop
SDA
0
0
0
1
0
A1
A0
1
AK
D7
D6
D5
D4
D3
D2
D1
D0 NAK
SCL
1
2
3
4
5
6
7
8
9
Read One Byte from Register
acknowledge
from LNBR
acknowledge
from LNBR
no acknowledge
from master
Start
Address
R
Status Data in Register 1
Status Data in Register 2
Stop
SDA
0
0
0
1
0
A1
A0
1
AK
D7
D6
D5
D4
D3
D2
D1
D0
AK
-
-
-
-
D3
D2
D1
D0 NAK
SCL
1
2
3
4
5
6
7
8
9
Read Multiple Bytes from Register
Figure 2. I 2 C? Interface. Read and write sequences.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
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