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参数资料
| 型号： | A8293SETTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 9/19页 |
| 文件大小： | 0K |
| 描述： | IC REG LNB BOOST/LINEAR 28QFN |
| 标准包装： | 9,000 |
| 应用： | 转换器，模拟和数字式卫星信号 STB 接收器/SatTV |
| 输入电压： | 9 V ~ 16 V |
| 输出数： | 1 |
| 输出电压： | 可调 |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VFQFN |
| 供应商设备封装： | 28-QFN |
| 包装： | 带卷 (TR) |
A8293
Single LNB Supply and Control Voltage Regulator
register 1, followed by register 2 if a further read is performed. If
the Read/Write bit is low, the master writes data to one of the two
Control registers. Note that multiple writes are not permitted. All
write operations must be preceded with the address.
The Acknowledge bit has two functions. It is used by the mas-
ter to determine if the slave device is responding to its address
and data, and it is used by the slave when the master is reading
data back from the slave. When the A8293 decodes the 7-bit ad-
dress field as a valid address, it responds by pulling SDA low
during the ninth clock cycle.
During a data write from the master, the A8293 also pulls SDA
low during the clock cycle that follows the data byte, in order to
indicate that the data has been successfully received. In both cas-
es, the master device must release the SDA line before the ninth
clock cycle, in order to allow this handshaking to occur.
During a data read, the A8293 acknowledges the address in the
same way as in the data write sequence, and then retains control
of the SDA line and send the data from register 1 to the master.
On completion of the eight data bits, the A8293 releases the SDA
line before the ninth clock cycle, in order to allow the master to
acknowledge the data. If the master holds the SDA line low dur-
ing this Acknowledge bit, the A8293 responds by sending the
data from register 2 to the master. Data bytes continue to be sent
to the master until the master releases the SDA line during the
Acknowledge bit. When this is detected, the A8293 stops sending
data and waits for a stop signal.
Interrupt Request
The A8293 also provides an interrupt request pin, IRQ, which
is an open-drain, active-low output. This output may be connect-
ed to a common IRQ line with a suitable external pull-up and can
be used with other I 2 C?-compatible devices to request attention
from the master controller.
The IRQ output becomes active when either the A8293 first
recognizes a fault condition, or at power-on, when the main sup-
ply, V IN , and the internal logic supply, V REG , reach the correct
operating conditions. It is only reset to inactive when the I 2 C?
master addresses the A8293 with the Read/Write bit set (caus-
ing a read). Fault conditions are indicated by the TSD, VUV, and
OCP bits, and are latched in the Status register. See the Status
register section for full description.
The DIS and PNG status bits do not cause an interrupt. The
PNG bit is continually updated, apart from the DIS bit, which
changes when the LNB is either disabled, faulted, or is enabled.
When the master recognizes an interrupt, it addresses all
slaves connected to the interrupt line in sequence, and then reads
the status register to determine which device is requesting atten-
tion. The A8293 latches all conditions in the Status register until
the completion of the data read. The action at the resampling
point is further defined in the Status Register section. The bits in
the Status register are defined such that the all-zero condition in-
dicates that the A8293 is fully active with no fault conditions.
When V IN is initially applied, the I 2 C?-compatible interface
does not respond to any requests until the internal logic supply
V REG has reached its operating level. Once V REG has reached this
point, the IRQ output goes active, and the VUV bit is set. After
the A8293 acknowledges the address, the IRQ flag is reset. After
the master reads the status registers, the registers are updated with
the VUV reset.
Start
Address
R
Status Register 1
Stop
SDA
0
0
0
1
0
A1
A0
1
AK
D7
D6
D5
D4
D3
D2
D1
D0 NAK
SCL
1
2
3
4
5
6
7
8
9
IRQ
Fault
Reload
Event
Read after Interrupt
Status Register
Figure 3. I 2 C? Interface. Read sequences after interrupt request.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
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