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参数资料
| 型号： | A8292SETTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 11/20页 |
| 文件大小： | 0K |
| 描述： | IC REG LNB SUPPLY/CONTROL 28-MLP |
| 标准包装： | 1 |
| 应用： | 转换器，模拟和数字式卫星信号接收器 |
| 输入电压： | 8 V ~ 16 V |
| 输出数： | 2 |
| 输出电压： | 12.7 V ~ 20.4 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VFQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN/MLP 裸露焊盘（5x5） |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1187-6 |
A8292
Dual LNB Supply and Control Voltage Regulator
During a data read, the A8292 acknowledges the address in the
same way as in the data write sequence, and then retains control
of the SDA line and send the data from register 1 to the master.
On completion of the eight data bits, the A8292 releases the SDA
line before the ninth clock cycle, in order to allow the master to
acknowledge the data. If the master holds the SDA line low dur-
ing this Acknowledge bit, the A8292 responds by sending the data
from register 2 to the master. Data bytes continue to be sent to the
master until the master releases the SDA line during the Acknowl-
edge bit. When this is detected, the A8292 stops sending data and
waits for a stop signal.
Interrupt Request
The A8292 also provides an interrupt request pin, IRQ, which is
an open-drain, active-low output. This output may be connected
to a common IRQ line with a suitable external pull-up and can
be used with other I 2 C?-compatible devices to request attention
from the master controller.
The IRQ output becomes active when either the A8292 first
recognizes a fault condition, or at power-on, when the main sup-
ply, V IN , and the internal logic supply, V REG , reach the correct
operating conditions. It is only reset to inactive when the I 2 C?
master addresses the A8292 with the Read/Write bit set (causing a
read). Fault conditions are indicated by the TSD, VUV, and OCP
bits, and are latched in the Status register. See the Status register
section for full description.
The DIS, PNG, CAD and TDET status bits do not cause an in-
terrupt. All these bits are continually updated, apart from the DIS
bit, which changes when the LNB is either disabled, intentionally
or due to a fault, or is enabled.
When the master recognizes an interrupt, it addresses all slaves
connected to the interrupt line in sequence, and then reads the
status register to determine which device is requesting attention.
The A8292 latches all conditions in the Status register until the
completion of the data read. The action at the resampling point is
further defined in the Status Register section. The bits in the Sta-
tus register are defined such that the all-zero condition indicates
that the A8292 is fully active with no fault conditions.
When V IN is initially applied, the I 2 C?-compatible interface
does not respond to any requests until the internal logic supply
V REG has reached its operating level. Once V REG has reached this
point, the IRQ output goes active, and the VUV bit is set. After the
A8292 acknowledges the address, the IRQ flag is reset. After the
master reads the status registers, the registers are updated with the
VUV reset.
Start
Address
R
Status Register 1
Stop
SDA
0
0
0
1
0
A1
A0
1
AK
D7
D6
D5
D4
D3
D2
D1
D0 NAK
SCL
1
2
3
4
5
6
7
8
9
IRQ
Fault
Reload
Event
Read after Interrupt
Status Register
Figure 4. I 2 C? Interface. Read sequences after interrupt request.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
11
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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