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| 型号： | A82DL32X4T |
| 厂商： | AMIC Technology Corporation |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| 中文描述： | 堆叠式多芯片封装（MCP）闪存和SRAM，A82DL32x4T（ü）32兆位（4Mx8 Bit/2Mx16位）的CMOS 3.3伏只，同时闪电行动 |
| 文件页数： | 27/60页 |
| 文件大小： | 931K |
| 代理商： | A82DL32X4T |
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A82DL32x4T(U) Series
PRELIMINARY
(August, 2005, Version 0.0)
26
AMIC Technology, Corp.
START
Write Program
Command
Sequence
Data Poll
from System
Verify Data
Last Address
Programming
Completed
No
Yes
Yes
Increment Address
Embedded
Program
algorithm in
progress
Note : See Table 14 for program command sequnce.
Figure 3. Program Operation
No
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program
bytes or words to a bank faster than using the standard
program command sequence. The unlock bypass command
sequence is initiated by first writing two unlock cycles. This is
followed by a third write cycle containing the unlock bypass
command, 20h. The device then enters the unlock bypass
mode. A two-cycle unlock bypass program command
sequence is all that is required to program in this mode. The
first cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the program
address and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two
unlock cycles required in the standard program command
sequence, resulting in faster total programming time. Table
12 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid. To
exit the unlock bypass mode, the system must issue the two-
cycle unlock bypass reset command sequence. The device
then returns to reading array data.
The device offers accelerated program operations through
the
WP
/ACC pin. When the system asserts V
HH
on the
WP
/ACC pin, the device automatically enters the Unlock
Bypass mode. The system may then write the two-cycle
Unlock Bypass program command sequence. The device
uses the higher voltage on the
WP
/ACC pin to accelerate
the operation. Note that the
WP
/ACC pin must not be at V
HH
any operation other than accelerated programming, or device
damage may result. In addition, the
WP
/ACC pin must not
be left floating or unconnected; inconsistent behavior of the
device may result.
Figure 3 illustrates the algorithm for the program operation.
Refer to the Erase and Program Operations table in the AC
Characteristics section for parameters, and Figure 15 for
timing diagrams.
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