参数资料
型号: A8514KLPTR-T
厂商: Allegro Microsystems Inc
文件页数: 14/42页
文件大小: 0K
描述: IC LED DVR WHT 4X80MA 16-ETSSOP
标准包装: 8,000
拓扑: PWM,SEPIC,升压(升压)
输出数: 4
内部驱动器:
类型 - 主要: 车载,背光
类型 - 次要: 白色 LED
频率: 580kHz ~ 2MHz
电源电压: 5 V ~ 40 V
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)裸露焊盘
供应商设备封装: 20-TSSOP-EP
包装: 带卷 (TR)
工作温度: -40°C ~ 125°C
A8514
Sync
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
The A8514 can also be synchronized using an external clock
on the FSET/SYNC pin. Figure 8 shows the correspondence of
V OUT
a sync signal and the FSET/SYNC pin, and figure 9 shows the
result when a sync signal is detected: the LED current does not
show any variation while the frequency changeover occurs. At
power-up if the FSET/SYNC pin is held low, the IC will not
power-up. Only when the FSET/SYNC pin is tri-stated to allow
the pin to rise, to about 1 V, or when a synchronization clock is
detected, will the A8514 try to power-up.
The basic requirement of the sync signal is 150 ns minimum on-
time and 150 ns minimum off time, as indicated by the specifica-
C1
C2
C3
I OUT
FSET/SYNC
SW node
tions for t PWSYNCON and t PWSYNCOFF . Figure 10 shows the timing
for a synchronization clock into the A8514 at 2.2 MHz. Thus any
pulse with a duty cycle of 33% to 66% at 2.2 MHz can be used to
synchronize the IC.
The SYNC pulse duty cycle ranges for selected switching fre-
quencies are:
C4
t
Figure 8. Diagram showing a synchronized FSET/SYNC pin and switch
node; shows V OUT (ch1, 20 V/div.), I OUT (ch2, 200 mA/div.), FSET/SYNC
(ch3, 2 V/div.), and SW node (ch4, 20 V/div.), time = 2 μ s/div.
V OUT
SYNC Pulse Frequency
(MHz)
2.2
2
1
Duty Cycle Range
(%)
33 to 66
30 to 70
15 to 85
C1
C2
I OUT
0.800
0.600
12 to 88
9 to 91
C3
2 MHz operation
FSET/SYNC
SW node
1 MHz operation
If during operation a sync clock is lost, the IC will revert to the
preset switching frequency that is set by the resistor R FSET . Dur-
ing this period the IC will stop switching for a maximum period
of about 7 μ s to allow the sync detection circuitry to switch over
to the externally preset switching frequency.
If the clock is held low for more than 7 μ s, the A8514 will shut
down. In this shutdown mode the IC will stop switching, the
C4
t
Figure 9. Transition of the SW waveform when the SYNC pulse is
detected. The A8514 switching at 2 MHz, applied SYNC pulse at 1 MHz;
shows V OUT (ch1, 20 V/div.), I OUT (ch2, 200 mA/div.), FSET/SYNC (ch3,
2 V/div.), and SW node (ch4, 20 V/div.), time = 5 μ s/div.
input disconnect switch is open, and the LEDs will stop sinking
current. To shutdown the IC into low power mode, the user must
t PWSYNCON
154 ns
disable the IC using the PWM pin, by keeping the pin low for a
period of 32,750 clock cycles. If the FSET/SYNC pin is released
at any time after 7 μ s, the A8514 will proceed to soft start.
150 ns
150 ns
t PWSYNCOFF
T = 454 ns
Figure 10. SYNC pulse on and off time requirements.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
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