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参数资料
| 型号： | A8514KLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 3/42页 |
| 文件大小： | 0K |
| 描述： | IC LED DVR WHT 4X80MA 16-ETSSOP |
| 标准包装： | 8,000 |
| 拓扑： | PWM，SEPIC，升压（升压） |
| 输出数： | 4 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 车载，背光 |
| 类型 - 次要： | 白色 LED |
| 频率： | 580kHz ~ 2MHz |
| 电源电压： | 5 V ~ 40 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 20-TSSOP-EP |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 125°C |
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A8514
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
GATE 1
VSENSE 2
VIN 3
20 SW
19 OVP
18 PGND
Pin-out Diagram
Terminal List Table
FAULT 4
COMP 5
APWM 6
PWM/EN 7
FSET/SYNC 8
ISET 9
AGND 10
17 PGND
16 PGND
15 VDD
14 LED1
13 LED2
12 LED3
11 LED4
Number
1
2
3
4
5
6
7
8
9
10
11,12,13,14
15
16,17.18
19
20
–
Name
GATE
VSENSE
VIN
ˉFˉ ˉA ˉ ˉUˉˉLˉ ˉTˉ
COMP
APWM
PWM/EN
FSET/SYNC
ISET
AGND
LEDx
VDD
PGND
OVP
SW
PAD
Function
Output gate driver pin for external P-channel FET control.
Connect this pin to the negative sense side of the current sense resistor R SC . The threshold
voltage is measured as V IN – V SENSE . There is also a fixed current sink to allow for trip
threshold adjustment.
Input power to the A8514 as well as the positive input used for current sense resistor.
Indicates a fault condition. Connect a 100 k Ω resistor between this pin and the required logic
level voltage. The pin is an open drain type configuration that will be pulled low when a fault
occurs.
Output of the error amplifier and compensation node. Connect a series R Z -C Z network from
this pin to ground for control loop compensation.
Analog trimming option for dimming. Applying a digital PWM signal to this pin adjusts the
internal I SET current.
PWM dimming pin, used to control the LED intensity by using pulse width modulation. Also
used to enable the A8514.
Frequency/synchronization pin. A resistor R FSET from this pin to ground sets the switching
frequency. This pin can also be used to synchronize two or more A8514s in the system. The
maximum synchronization frequency is 2.3 MHz.
Connect the R ISET resistor between this pin and ground to set the 100% LED current.
LED signal ground.
Connect the cathodes of the LED strings to these pins.
Output of internal LDO; connect a 0.1 μ F decoupling capacitor between this pin and ground.
Power ground for internal DMOS device.
Overvoltage Condition (OVP) sense; connect the R OVP resistor from V OUT to this pin to
adjust the overvoltage protection.
The drain of the internal DMOS switch of the boost converter.
Exposed pad of the package providing enhanced thermal dissipation. This pad must be
connected to the ground plane(s) of the PCB with at least 8 vias, directly in the pad.
Thermal Characteristics may require derating at maximum conditions, see application information
On 2-layer PCB, 3 in.
Characteristic
Package Thermal Resistance
Symbol
R θ JA
Test Conditions*
2
On 4-layer PCB based on JEDEC standard
(estimated)
Value
40.0
29.0
Unit
oC/W
oC/W
*Additional thermal information available on the Allegro website
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
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