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参数资料
| 型号： | A8514KLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 23/42页 |
| 文件大小： | 0K |
| 描述： | IC LED DVR WHT 4X80MA 16-ETSSOP |
| 标准包装： | 8,000 |
| 拓扑： | PWM，SEPIC，升压（升压） |
| 输出数： | 4 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 车载，背光 |
| 类型 - 次要： | 白色 LED |
| 频率： | 580kHz ~ 2MHz |
| 电源电压： | 5 V ~ 40 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 20-TSSOP-EP |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 125°C |
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A8514
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
? 2X current limit If the input current level goes above 2X of the
preset current limit threshold, the A8514 will shut down in less
than 3 μ s regardless of user input (figure 31). This is a latched
condition. The Fault flag is also set to indicate a fault. This
feature is meant to prevent catastrophic failure in the system due
to inductor short to ground, switch pin short to ground, or output
short to ground.
Setting the current sense resistor
The typical threshold for the current sense circuit is 104 mV,
V IN
when R ADJ is 0 Ω . This voltage can be trimmed by the R ADJ
resistor. The typical 1X trip point should be set at about 3 A,
which coincides with the cycle-by-cycle current limit minimum
threshold.
For example, given 3 A of input current, and the calculated maxi-
mum value of the sense resistor, R SC = 0.033 Ω .
The R SC chosen is 0.03 Ω , a standard.
C1
C2
C3
C4
t
I OUT
V DD
PWM/EN
Also:
R ADJ = ( V SENSETRIP – V ADJ ) / I ADJ
(7)
Figure 32. Shutdown showing a falling input voltage (V IN ); shows V IN
(ch1, 2 V/div.), I OUT (ch2, 200 mA/div.), V DD (ch3, 5 V/div.), and PWM/EN
(ch4, 2 V/div.), time = 5 ms/div.
The trip point voltage is calculated as:
V ADJ = 3.0 A × 0.03 Ω = 0.090 V
R ADJ = (0.104 – 0.09 V) / (20.3 μ A) = 731 Ω
GATE
Input UVLO
C1
When V IN and V SENSE rise above the V UVLOrise threshold, the
A8514 is enabled. A8514 is disabled when V IN falls below the
V UVLOfall threshold for more than 50 μ s. This small delay is used
to avoid shutting down because of momentary glitches in the
input power supply. When V IN falls below 4.35 V, the IC will
shut down (see figure 32).
C2
C3
I OUT
V DD
VDD
The VDD pin provides regulated bias supply for internal circuits.
Connect the capacitor C VDD with a value of 0.1 μ F or greater to
this pin. The internal LDO can deliver no more than 2 mA of cur-
rent with a typical V DD of about 3.5 V, enabling this pin to serve
as the pull-up voltage for the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ pin.
Shutdown
If the PWM/EN pin is pulled low for more than t PWML (32,750
clock cycles), the device enters shutdown mode and clears all
PWM/EN
C4
t
Figure 33. Shutdown using the enable function, showing the 16 ms
delay between the PWM/EN signal and when the VDD and GATE of
the disconnect switch turns off; shows GATE (ch1, 10 V/div.), I OUT (ch2,
200 mA/div.), V DD (ch3, 5 V/div.), and PWM/EN (ch4, 2 V/div.), time = 5
ms/div.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
23
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