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| 型号： | AD1871YRSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC STEREO AUDIO 24BIT 28SSOP |
| 产品培训模块： | Interfacing AV Converters to Blackfin Processors |
| 标准包装： | 47 |
| 位数： | 24 |
| 采样率（每秒）： | 96k |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 2 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 28-SSOP |
| 包装： | 管件 |
| 输入数目和类型： | 4 个单端，单极 |
| 产品目录页面： | 777 (CN2011-ZH PDF) |
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AD1871
–12–
REV. 0
TERMINOLOGY
Dynamic Range
The ratio of a full-scale input signal to the integrated input
noise in the pass band (20 Hz to 20 kHz), expressed in decibels
(dB). Dynamic range is measured with a –60 dB input signal
and is equal to (S/[THD+N]) + 60 dB. Note that spurious
harmonics are below the noise with a –60 dB input, so the
noise level establishes the dynamic range. The dynamic range
is specified with and without an A-Weight filter applied.
Signal to (Total Harmonic Distortion + Noise)
(S/[THD+N])
The ratio of the root-mean-square (rms) value of the fundamen-
tal input signal to the rms sum of all other spectral components
in the pass band, expressed in decibels (dB).
Pass Band
The region of the frequency spectrum unaffected by the attenu-
ation of the digital decimator’s filter.
Pass-Band Ripple
The peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the pass band, expressed
in decibels.
Stop Band
The region of the frequency spectrum attenuated by the digital
decimator’s filter to the degree specified by stop-band attenuation.
Gain Error
With a near full-scale input, the ratio of the actual output to the
expected output, expressed as a percentage.
Interchannel Gain Mismatch
With identical near full-scale inputs, the ratio of the outputs of
the two stereo channels, expressed in decibels.
Gain Drift
Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per
∞C.
Crosstalk (EIAJ Method)
Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine-wave input on the other channel, expressed
in decibels.
Power Supply Rejection
With no analog input, signal present at the output when a
300 mV p-p signal is applied to power supply pins, expressed in
decibels of full scale.
Group Delay
Intuitively, the time interval required for an input pulse to
appear at the converter’s output, expressed in milliseconds (ms).
More precisely, the derivative of radian phase with respect to
radian frequency at a given frequency.
GLOSSARY
ADC—Analog-to-Digital Converter
DSP—Digital Signal Processor
IMCLK—Internal master clock signal, used to clock the deci-
mating filter section. (Its frequency must be 256
fS.)
MCLK—External master clock signal applied to the AD1871.
Its frequency can be 256, 512, or 768
fS. MCLK is divided
internally to give an IMCLK frequency that must be 256
fS.
MODCLK—This is the -
modulator clock that determines
the sample rate of the modulator. Ideally, it should not exceed
the lower of 6.144 MHz or 128
fS. The MODCLK is derived
from the IMCLK by a divider that can be selected as /2 or /4.
MUX—Multiplexer
PGA—Programmable Gain Amplifier
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD1871YRSZ | 制造商:Analog Devices 功能描述:IC, ADC, 24BIT, 96KHZ, SSOP-28 |
| AD1871YRSZ-REEL | 功能描述:IC ADC STEREO 24BIT 96KHZ 28SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
| AD1876 | 制造商:AD 制造商全称:Analog Devices 功能描述:16-Bit 100 kSPS Sampling ADC |
| AD1876JN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1877 | 制造商:AD 制造商全称:Analog Devices 功能描述:Single-Supply 16-Bit Stereo ADC |
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