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| 型号： | AD5161BRM5-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/20页 |
| 文件大小： | 0K |
| 描述： | IC DGTL POT SPI 256POS 10-MSOP |
| 标准包装： | 1,000 |
| 接片： | 256 |
| 电阻（欧姆）： | 5k |
| 电路数： | 1 |
| 温度系数： | 标准值 45 ppm/°C |
| 存储器类型： | 易失 |
| 接口： | I²C，SPI |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 带卷 (TR) |
Data Sheet
AD5161
Rev. B | Page 5 of 20
TIMING CHARACTERISTICS—5 k, 10 k, 50 k, 100 k VERSIONS
VDD = +5V ± 10%, or +3V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.
Table 3.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
SPI INTERFACE TIMING CHARACTERISTICS6, 10 (Specifications Apply to All Parts)
Clock Frequency
f
CLK
25
MHz
Input Clock Pulsewidth
t
CH, tCL
Clock level high or low
20
ns
Data Setup Time
t
DS
5
ns
Data Hold Time
t
DH
5
ns
CS Setup Time
t
CSS
15
ns
CS High Pulsewidth
t
CSW
40
ns
CLK Fall to CS Fall Hold Time
t
CSH0
0
ns
CLK Fall to CS Rise Hold Time
t
CSH1
0
ns
CS Rise to Clock Rise Setup
t
CS1
10
ns
SCL Clock Frequency
f
SCL
400
kHz
t
BUF Bus Free Time between STOP and START
t
1
1.3
s
t
HD;STA Hold Time (Repeated START)
t
2
After this period, the first clock pulse is
generated.
0.6
s
t
LOW Low Period of SCL Clock
t
3
1.3
s
t
HIGH High Period of SCL Clock
t
4
0.6
50
s
t
SU;STA Setup Time for Repeated START Condition
t
5
0.6
s
t
HD;DAT Data Hold Time
t
6
0.9
s
t
SU;DAT Data Setup Time
t
7
100
ns
t
F Fall Time of Both SDA and SCL Signals
t
8
300
ns
t
R Rise Time of Both SDA and SCL Signals
t
9
300
ns
t
SU;STO Setup Time for STOP Condition
t
10
0.6
s
NOTES
1 Typical specifications represent average readings at +25°C and V
DD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 V
AB = VDD, Wiper (VW) = no connect.
4 INL and DNL are measured at V
W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8 P
DISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9 All dynamic characteristics use V
DD = 5 V.
10 See timing diagram for location of measured values. All input control voltages are specified with t
R = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V.
11 See timing diagrams for locations of measured values.
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| AD5161BRMZ10 | 功能描述:IC DGTL POT SPI 10K 10-MSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 接片:256 电阻（欧姆）:100k 电路数:1 温度系数:标准值 35 ppm/°C 存储器类型:非易失 接口:3 线串口 电源电压:2.7 V ~ 5.25 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WDFN 裸露焊盘 供应商设备封装:8-TDFN-EP（3x3） 包装:剪切带 (CT) 产品目录页面:1399 (CN2011-ZH PDF) 其它名称:MAX5423ETA+TCT |
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