参数资料
型号: AD5273EVAL
厂商: Analog Devices Inc
文件页数: 10/24页
文件大小: 0K
描述: BOARD EVAL FOR AD5273
标准包装: 1
主要目的: 数字电位器
已用 IC / 零件: AD5273
已供物品:
相关产品: AD5273BRJZ10-R7DKR-ND - IC DGTL POT 64P 10K OTP SOT23-8
AD5273BRJZ50-REEL7TR-ND - IC POT DGTL 50K 64POS SOT23
AD5273BRJZ100-R7TR-ND - IC POT DGTL 1K 64POS SOT23
AD5273BRJZ1-REEL7TR-ND - IC POT DGTL 1K 64POS SOT23
AD5273BRJZ10-R7CT-ND - IC DGTL POT 64P 10K OTP SOT23-8
AD5273BRJZ10-R7TR-ND - IC DGTL POT 64P 10K OTP SOT23-8
AD5273BRJ10-R2CT-ND - IC DGTL POT 10K 64POS SOT23-8
AD5273BRJ1-R2CT-ND - IC DGTL POT 1K 64POS SOT23-8
AD5273BRJ100-R2CT-ND - IC DGTL POT 100K 64POS SOT23-8
AD5273BRJ50-R2CT-ND - IC DGTL POT 50K 64POS SOT23-8
AD5273
Rev. H | Page 18 of 24
4.
When all data bits have been read or written, a stop con-
dition is established by the master. A stop condition is
defined as a low-to-high transition on the SDA line
while SCL is high. In write mode, the master pulls the
SDA line high during the 10th clock pulse to establish a
stop condition, as shown in Figure 42 and Figure 43. In
read mode, the master issues a no acknowledge for the
ninth clock pulse, that is, the SDA line remains high. The
master then brings the SDA line low before the 10th clock
pulse, which goes high to establish a stop condition, as
shown in Figure 44.
A repeated write function gives the user flexibility to
update the RDAC output continuously, except after
permanent programming, when the part is addressed and
receives instructions only once. During the write cycle,
each data byte updates the RDAC output. For example,
after the RDAC has acknowledged its slave address and
instruction bytes, the RDAC output updates after these two
bytes. If another byte is written to the RDAC while it is still
addressed to a specific slave device with the same instruc-
tion, this byte updates the output of the selected slave device.
If different instructions are needed, the write mode must
be started again with a new slave address, instruction, and
data bytes. Similarly, a repeated read function of the RDAC
is also allowed.
CONTROLLING TWO DEVICES ON ONE BUS
Figure 45 shows two AD5273 devices on the same serial bus.
Each has a different slave address because the state of each AD0
pin is different. This allows each device to operate independently.
The master device output bus line drivers are open-drain pull-
down in a fully I2C-compatible interface.
MASTER
SDA SCL
AD0
AD5273
SDA SCL
AD0
AD5273
SDA
SCL
5V
RP
5V
03
22
4-
04
5
Figure 45. Two AD5273 Devices on One Bus
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