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参数资料
| 型号： | AD5320BRT-500RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/20页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT R-R W/BUFF SOT23-6 |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1 |
| 设置时间： | 8µs |
| 位数： | 12 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-6 |
| 供应商设备封装： | SOT-23-6 |
| 包装： | 标准包装 |
| 输出数目和类型： | 1 电压，双极 |
| 采样率（每秒）： | 125k |
| 其它名称： | AD5320BRT500RL7DKR |
AD5320
Rev. C | Page 13 of 20
POWER-DOWN MODES
The AD5320 contains four separate modes of operation. These
modes are software-programmable by setting two bits (DB13
and DB12) in the control register. Table 5 shows how the state
of the bits corresponds to the mode of operation of the device.
Table 5. Modes of Operation for the AD5320
DB13
DB12
Operating Mode
0
Normal Operation
Power-Down Modes
0
1
1 kΩ to GND
1
0
100 kΩ to GND
1
Three-State
When both bits are set to 0, the part works with its normal power
consumption of 140 μA at 5 V. However, for the three power-down
modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not
only does the supply current fall, but the output stage is also inter-
nally switched from the output of the amplifier to a resistor net-
work of known values. This has the advantage that the output
impedance of the part is known while the part is in power-down
mode. There are three different options: the output is connected
internally to GND through a 1 kΩ resistor, the output is connected
internally to GND through a 100 kΩ resistor, or it is left open-
circuited (three-state). The output stage is illustrated in Figure 27.
RESISTOR
STRING DAC
RESISTOR
NETWORK
POWER-DOWN
CIRCUITRY
VOUT
00
93
4-
02
6
AMPLIFIER
Figure 27. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down. The time to exit power-
down is typically 2.5 μs for VDD = 5 V and 5 μs for VDD = 3 V
(see Figure 21).
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