- 您现在的位置：买卖IC网 > PDF目录373878 > AD5390BCP-3-REEL (ANALOG DEVICES INC) 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs PDF资料下载
参数资料
| 型号： | AD5390BCP-3-REEL |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | DAC |
| 英文描述： | 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs |
| 中文描述： | SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, QCC64 |
| 封装： | 9 X 9 MM, MO-220VMMD-4, LFCSP-64 |
| 文件页数： | 26/44页 |
| 文件大小： | 1319K |
| 代理商： | AD5390BCP-3-REEL |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页当前第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页
AD5390/AD5391/AD5392
Standalone Mode
By connecting the daisy-chain enable (DCEN) pin low,
standalone mode is enabled. The serial interface works with
both a continuous and a noncontinuous serial clock. The first
falling edge of SYNC starts the write cycle and resets a counter
that counts the number of serial clocks to ensure that the
correct number of bits is shifted into the serial shift register.
Any further edges on SYNC except for a falling edge are
ignored until 24 bits are clocked in. Once 24 bits have been
shifted in, the SCLK is ignored. For another serial transfer to
take place, the counter must be reset by the falling edge of
SYNC.
Daisy-Chain Mode
For systems that contain several devices, the SDO pin can be
used to daisy-chain the devices together. This daisy-chain mode
can be useful in system diagnostics and for reducing the
number of serial interface lines.
Rev. A | Page 26 of 44
By connecting the DCEN pin high, daisy-chain mode is
enabled. The first falling edge of SYNC starts the write cycle.
The SCLK is continuously applied to the input shift register
when SYNC is low. If more than 24 clock pulses are applied,
the data ripples out of the shift register and appears on the SDO
line. This data is clocked out on the rising edge of SCLK and is
valid on the falling edge. By connecting the SDO of the first
device to the DIN input on the next device in the chain, a
multidevice interface is constructed. For each device in the
system, 24 clock pulses are required. Therefore, the total
number of clock cycles must equal 24
N
where
N
is the total
number of AD539x devices in the chain.
When the serial transfer to all devices is complete, SYNC is
taken high. This latches the input data in each device in the
daisy chain and prevents any further data from being clocked
into the input shift register.
If SYNC is taken high before 24 clocks are clocked into the part,
it is considered a bad frame and the data is discarded.
The serial clock can be either a continuous or a gated clock. A
continuous SCLK source can be used only if the SYNC can be
held low for the correct number of clock cycles. In gated clock
mode, a burst clock containing the exact number of clock cycles
must be used and SYNC taken high after the final clock to latch
the data.
Readback Mode
Readback mode is invoked by setting the R/W bit = 1 in the
serial input register write sequence. With R/W = 1, Bits A3 to A0
in association with Bits REG1 and REG0 select the register to be
read. The remaining data bits in the write sequence are don’t
care bits. During the next SPI write, the data appearing on the
SDO output contains the data from the previously addressed
register. For a read of a single register, the NOP command can
be used in clocking out the data from the selected register on
SDO.
The readback diagram in Figure 32 shows the readback
sequence. For example, to read back the m register of Channel 0
on the AD539x, the following sequence should be implemented.
First, write 0x404XXX to the AD539x input register. This
configures the AD539x for read mode with the m register of
Channel 0 selected. Note that all Data Bits DB13 to DB0 are
don’t care bits. Follow this with a second write, a NOP
condition, and 0x000000. During this write, the data from the m
register is clocked out on the DOUT line—that is, data clocked
out contains the data from the m register in Bits DB13 to DB0,
and the top 10 bits contain the address information as
previously written. In readback mode, the SYNC signal must
frame the data. Data is clocked out on the rising edge of SCLK
and is valid on the falling edge of the SCLK signal. If the SCLK
idles high between the write and read operations of a readback,
then the first bit of data is clocked out on the falling edge of
SYNC.
0
24
48
SCLK
SYNC
DIN
SDO
UNDEFINED
SELECTED REGISTER DATA CLOCKED OUT
NOP CONDITION
INPUT WORD SPECIFIES REGISTER TO BE READ
DB23
DB0
DB0
DB23
DB23
DB0
DB0
DB23
Figure 32. AD539x Readback Operation
相关PDF资料 |
PDF描述 |
|---|---|
| AD5391BCP-3-REEL | 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs |
| AD5391BST-3 | 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs |
| AD5391BST-5 | 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs |
| AD5391BST-5-REEL | 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs |
| AD5392 | 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD5390BCP-3-REEL7 | 制造商:Analog Devices 功能描述:DAC 16-CH Resistor-String 14-bit 64-Pin LFCSP EP T/R |
| AD5390BCP-5 | 制造商:Analog Devices 功能描述:DAC 16-CH Resistor-String 14-bit 64-Pin LFCSP EP 制造商:Analog Devices 功能描述:14BIT DAC 16CH 5V 5390 LFCSP-64 |
| AD5390BCP-5-REEL | 制造商:Analog Devices 功能描述:DAC 16-CH Resistor-String 14-bit 64-Pin LFCSP EP T/R |
| AD5390BCP-5-REEL7 | 制造商:Analog Devices 功能描述:DAC 16-CH Resistor-String 14-bit 64-Pin LFCSP EP T/R |
| AD5390BCP-U1 | 制造商:Analog Devices 功能描述:DAC HEXADECIMAL RES-STRING 14BIT 64LFCSP - Bulk |
发布紧急采购，3分钟左右您将得到回复。