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参数资料
| 型号： | AD5428YRUZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/33页 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT MULTIPLYING 20TSSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 2,500 |
| 设置时间： | 30ns |
| 位数： | 8 |
| 数据接口： | 并联 |
| 转换器数目： | 2 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 3.3µW |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 2 电流，单极；2 电流，双极 |
| 采样率（每秒）： | 21.3M |
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AD5428/AD5440/AD5447
Data Sheet
Rev. C | Page 22 of 32
PARALLEL INTERFACE
Data is loaded into the AD5428/AD5440/AD5447 in 8-, 10-, or
12-bit parallel word format. Control lines CS and R/W allow
data to be written to or read from the DAC register. A write
event takes place when CS and R/W are brought low, data
available on the data lines fills the shift register, and the rising
edge of CS latches the data and transfers the latched data-word
to the DAC register. The DAC latches are not transparent;
therefore, a write sequence must consist of a falling and rising
edge on CS to ensure that data is loaded into the DAC register
and its analog equivalent is reflected on the DAC output.
A read event takes place when R/W is held high and CS is
brought low. Data is loaded from the DAC register, goes back
into the input register, and is output onto the data line, where it
can be read back to the controller for verification or diagnostic
purposes. The input and DAC registers of these devices are not
transparent; therefore, a falling and rising edge of CS is required
to load each data-word.
MICROPROCESSOR INTERFACING
ADSP-21xx-to-AD5428/AD5440/AD5447 Interface
Figure 44 shows the AD5428/AD5440/AD5447 interfaced to
the ADSP-21xx series of DSPs as a memory-mapped device. A
single wait state may be necessary to interface the AD5428/
AD5440/AD5447 to the ADSP-21xx, depending on the clock
speed of the DSP. The wait state can be programmed via the
data memory wait state control register of the ADSP-21xx (see
the ADSP-21xx family’s user manual for details).
04462-
055
R/W
DB0 TO DB11
AD5428/
AD5440/
AD54471
ADDRESS
DECODER
CS
DATA 0 TO
DATA 23
ADDRESS BUS
ADDR0 TO
ADRR13
ADSP-21xx1
DATA BUS
DMS
WR
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 44. ADSP21xx-to-AD5428/AD5440/AD5447 Interface
8xC51-to-AD5428/AD5440/AD5447 Interface
Figure 45 shows the interface between the AD5428/AD5440/
AD5447 and the 8xC51 family of DSPs. To facilitate external
data memory access, the address latch enable (ALE) mode is
enabled. The low byte of the address is latched with this output
pulse during access to the external memory. AD0 to AD7 are
the multiplexed low order addresses and data bus, and they
require strong internal pull-ups when emitting 1s. During
access to external memory, A8 to A15 are the high order
address bytes. Because these ports are open drain, they also
require strong internal pull-ups when emitting 1s.
04462-
057
R/W
DB0 TO DB11
AD5428/
AD5440/
AD54471
ADDRESS
DECODER
CS
AD0 TO AD7
ADDRESS BUS
A8 TO A15
80511
DATA BUS
WR
1ADDITIONAL PINS OMITTED FOR CLARITY.
8-BIT
LATCH
ALE
Figure 45. 8xC51-to-AD5428/AD5440/AD5447 Interface
ADSP-BF5xx-to-AD5428/AD5440/AD5447 Interface
Figure 46 shows a typical interface between the AD5428/
AD5440/AD5447 and the ADSP-BF5xx family of DSPs. The
asynchronous memory write cycle of the processor drives the
digital inputs of the DAC. The AMSx line is actually four
memory select lines. Internal ADDR lines are decoded into
AMS3–0, and then these lines are inserted as chip selects. The
rest of the interface is a standard handshaking operation.
04462-
056
R/W
DB0 TO DB11
AD5428/
AD5440/
AD54471
ADDRESS
DECODER
CS
DATA 0 TO
DATA 23
ADDRESS BUS
ADDR1 TO
ADRR19
ADSP-BF5xx1
DATA BUS
AMSx
AWE
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 46. ADSP-BF5xx-to-AD5428/AD5440/AD5447 Interface
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相关代理商/技术参数 |
参数描述 |
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| AD5428YRUZ-REEL7 | 功能描述:IC DAC 8BIT MULTIPLYING 20TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 设计资源:Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052) Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053) AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054) Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055) Single Supply Low Noise LED Current Source Driver Using a Current Output DAC in the Reverse Mode (CN0139) 标准包装:10,000 系列:- 设置时间:- 位数:12 数据接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 转换器数目:1 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:SOT-23-8 薄型，TSOT-23-8 供应商设备封装:TSOT-23-8 包装:带卷 (TR) 输出数目和类型:1 电流，单极；1 电流，双极 采样率（每秒）:2.7M |
| AD5429 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface |
| AD5429_13 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Serial Interface |
| AD5429YRU | 功能描述:IC DAC DUAL 8BIT MULT 16-TSSOP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色产品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 标准包装:91 系列:- 设置时间:4µs 位数:10 数据接口:MICROWIRE?，串行，SPI? 转换器数目:8 电压电源:单电源 功率耗散（最大）:2.7mW 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:14-WFDFN 裸露焊盘 供应商设备封装:14-DFN-EP（4x3） 包装:管件 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD5429YRU-REEL | 功能描述:IC DAC DUAL 8BIT MULT 16-TSSOP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 设计资源:Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052) Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053) AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054) Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055) Single Supply Low Noise LED Current Source Driver Using a Current Output DAC in the Reverse Mode (CN0139) 标准包装:10,000 系列:- 设置时间:- 位数:12 数据接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 转换器数目:1 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:SOT-23-8 薄型，TSOT-23-8 供应商设备封装:TSOT-23-8 包装:带卷 (TR) 输出数目和类型:1 电流，单极；1 电流，双极 采样率（每秒）:2.7M |
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