参数资料
型号: AD5428YRUZ-REEL
厂商: Analog Devices Inc
文件页数: 8/33页
文件大小: 0K
描述: IC DAC 8BIT MULTIPLYING 20TSSOP
产品培训模块: Data Converter Fundamentals
DAC Architectures
标准包装: 2,500
设置时间: 30ns
位数: 8
数据接口: 并联
转换器数目: 2
电压电源: 单电源
功率耗散(最大): 3.3µW
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 20-TSSOP
包装: 带卷 (TR)
输出数目和类型: 2 电流,单极;2 电流,双极
采样率(每秒): 21.3M
Data Sheet
AD5428/AD5440/AD5447
Rev. C | Page 15 of 32
TERMINOLOGY
Relative Accuracy (Endpoint Nonlinearity)
A measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function. It
is measured after adjusting for zero and full scale and is
typically expressed in LSBs or as a percentage of the full-scale
reading.
Differential Nonlinearity
The difference in the measured change and the ideal 1 LSB
change between two adjacent codes. A specified differential
nonlinearity of 1 LSB maximum over the operating
temperature range ensures monotonicity.
Gain Error (Full-Scale Error)
A measure of the output error between an ideal DAC and the
actual device output. For these DACs, ideal maximum output is
VREF – 1 LSB. The gain error of the DACs is adjustable to zero
with an external resistance.
Output Leakage Current
The current that flows into the DAC ladder switches when they
are turned off. For the IOUT1 terminal, it can be measured by
loading all 0s to the DAC and measuring the IOUT1 current.
Minimum current flows into the IOUT2 line when the DAC is
loaded with all 1s.
Output Capacitance
Capacitance from IOUT1 or IOUT2 to AGND.
Output Current Settling Time
The amount of time for the output to settle to a specified level
for a full-scale input change. For these devices, it is specified
with a 100 Ω resistor to ground.
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-sec or nV-sec,
depending on whether the glitch is measured as a current or
voltage signal.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs is capacitively coupled through the
device and produces noise on the IOUT pins and, subsequently,
on the following circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
The error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal when all 0s are
loaded to the DAC.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics are included,
such as second to fifth harmonics.
1
5
4
3
2
V
THD
2
log
20
+
=
Digital Intermodulation Distortion
Second-order intermodulation distortion (IMD) measurements
are the relative magnitude of the fa and fb tones digitally generated
by the DAC and the second-order products at 2fa fb and
2fb fa.
Spurious-Free Dynamic Range (SFDR)
SFDR is the usable dynamic range of a DAC before spurious
noise interferes or distorts the fundamental signal. SFDR is the
measure of difference in amplitude between the fundamental
and the largest harmonic or nonharmonic spur from dc to full
Nyquist bandwidth (half the DAC sampling rate, or fs/2).
Narrow-band SFDR is a measure of SFDR over an arbitrary
window size, in this case 50%, of the fundamental. Digital SFDR
is a measure of the usable dynamic range of the DAC when the
signal is a digitally generated sine wave.
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