参数资料
型号: AD5428YRUZ-REEL
厂商: Analog Devices Inc
文件页数: 2/33页
文件大小: 0K
描述: IC DAC 8BIT MULTIPLYING 20TSSOP
产品培训模块: Data Converter Fundamentals
DAC Architectures
标准包装: 2,500
设置时间: 30ns
位数: 8
数据接口: 并联
转换器数目: 2
电压电源: 单电源
功率耗散(最大): 3.3µW
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 20-TSSOP
包装: 带卷 (TR)
输出数目和类型: 2 电流,单极;2 电流,双极
采样率(每秒): 21.3M
Data Sheet
AD5428/AD5440/AD5447
Rev. C | Page 9 of 32
04462-006
R/W
CS
1
2
3
4
5
6
7
8
9
10
20
21
22
23
24
19
18
17
16
15
14
13
12
11
IOUTA
RFBA
VREFA
DB11
DAC A/B
DGND
AGND
RFBB
VREFB
VDD
DB0 (LSB)
DB10
DB9
DB6
DB7
DB8
DB1
DB2
DB5
DB4
DB3
IOUTB
AD5447
TOP VIEW
(Not to Scale)
Figure 6. Pin Configuration 24-Lead TSSOP (RU-24)
Table 6. AD5447 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
AGND
DAC Ground Pin. This pin should typically be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
2, 24
IOUTA, IOUTB
DAC Current Outputs.
3, 23
RFBA, RFBB
DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to an external amplifier
output.
4, 22
VREFA, VREFB
DAC Reference Voltage Input Terminals.
5
DGND
Digital Ground Pin.
6
DAC A/B
Selects DAC A or DAC B. Low selects DAC A; high selects DAC B.
7 to 18
DB11 to DB0
Parallel Data Bits 11 Through 0.
19
CS
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read
data from the DAC register.
20
R/W
Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with
CS to read back the contents of the DAC register. When CS and R/W are held low, the latches are transparent.
Any changes on the data lines are reflected in the relevant DAC output.
21
VDD
Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
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