参数资料
型号: AD652JP
厂商: Analog Devices Inc
文件页数: 13/28页
文件大小: 779K
描述: IC V-F CONV SYNCH MONO 5V 20PLCC
标准包装: 1
类型: 电压至频率
频率 - 最大: 2MHz
全量程: ±25ppm/°C
线性: ±0.005%
安装类型: 表面贴装
封装/外壳: 20-LCC(J 形引线)
供应商设备封装: 20-PLCC(9x9)
包装: 管件
 
AD652
 
Rev. C | Page 13 of 28
The one-shot capacitor controls the pulse width of the
frequency output. The pulse is initiated by the rising edge of the
clock signal. The delay time between the rising edge of the clock
and the falling edge of the frequency output is typically 200 ns.
The width of the pulse is 5 ns/pF, and the minimum width is
about 200 ns with Pin 9 floating. If the one-shot period is
accidentally chosen longer than the clock period, the width of
the pulse defaults to equal the clock period. The one-shot can be
disabled by connecting Pin 9 to +VS (Figure 17); the output
pulse width is then equal to the clock period. The one-shot is
activated (Figure 18) by connecting a capacitor from Pin 9 to
+V
S
, V
S,
 or Digital Ground (+V
S
 is preferred).
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ONE
SHOT
AND
"D"
FLOP
Q CK
D
Q
1mA
20k&
AD652
SYNCHRONOUS
VOLTAGE-TO-
FREQUENCY
CONVERTER
5V
REFERENCE
+V
S
 
Figure 17. One-Shot Disabled
 
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ONE
SHOT
AND
"D"
FLOP
Q CK
D
Q
1mA
20k&
AD652
SYNCHRONOUS
VOLTAGE-TO-
FREQUENCY
CONVERTER
5V
REFERENCE
C
OS
ANY AC GND
(+V
S
,V
S
, OR DIGITAL GND)
 
Figure 18. One-Shot Enabled
DIGITAL GROUND
Digital Ground can be at any potential between V
S
 and
(+V
S
  4 V). This can be very useful in systems with derived
grounds rather than stiff supplies. For example, in a small
isolated power circuit, often only a single supply is generated
and the ground is set by a divider tap. Such a ground cannot
handle the large currents associated with digital signals. With
the AD652 SVFC, it is possible to connect the Digital Ground to
V
S
 for a solid logic reference, as shown in Figure 19.
+V
S
1
2
3
4

+
5
6
7
V
IN
8
16
15
14
13
12
11
10
9
ONE
SHOT
AND
"D"
FLOP
Q CK
D
Q
1mA
20k&
AD652
SYNCHRONOUS
VOLTAGE-TO-
FREQUENCY
CONVERTER
5V
REFERENCE
R
L
5V
CLOCK
FREQ
OUT
C
INT
C
OS
V
S
 
Figure 19. Digital GND at VS 
 
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