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参数资料
型号： AD6600ST
厂商： Analog Devices, Inc.
英文描述： Dual Channel, Gain-Ranging ADC with RSSI
中文描述： 双通道，增益测距型ADC的RSSI
文件页数： 3/24页
文件大小： 303K
代理商： AD6600ST
REV. 0
–3–
AD6600
TIMING REQUIREMENTS AND SWITCHING SPECIFICATIONS
1
(AVCC = 5 V, DVCC = 3.3 V; ENC and
ENC
= 20 MSPS; T
MIN
= –40 C, T
MAX
= +85 C unless otherwise noted.)
Test
Level
AD6600AST
Typ
Parameter
Name
Temp
Min
Max
Unit
A/D CONVERTER
Conversion Rate
Maximum Conversion Rate
Minimum Conversion Rate
Aperture Uncertainty
ENCODE INPUTS (ENC,
ENC
)
2
Period
Pulsewidth High
3
Pulsewidth Low
4
2
×
CLOCK OUTPUT (CLK2
×
)
5
Output Frequency
Output Period
6
f
ENC
1/(t
ENC
)
MSPS
MSPS
MSPS
ps rms
Full
Full
25
°
C
II
IV
V
20
6
t
j
0.3
t
ENC
t
ENCH
t
ENCL
Full
Full
Full
II
IV
IV
50
20
20
ns
ns
ns
2
×
f
ENC
t
ENCL
t
ENCH
t
ENCH
/2
3
2.6
MSPS
ns
ns
ns
ns
ns
t
CLK2
×
_1
t
CLK2
×
_2
t
CLK2
×
L
Full
Full
Full
Full
Full
V
V
V
V
V
CLK2
×
Pulsewidth Low
6
Output Risetime
7
Output Falltime
7
OUTPUT RISE/FALL TIMES
8
Output Risetime (D10:D0, RSSI2:0)
Output Falltime (D10:D0, RSSI2:0)
Output Risetime (AB_OUT)
Output Falltime (AB_OUT)
Full
Full
Full
Full
V
V
V
V
8
8.4
6
6.2
ns
ns
ns
ns
NOTES
1
See AD6600 Timing Diagrams.
2
All switching specifications tested by driving ENC and
ENC
differentially.
3
Several timing specifications are a function of Encode high time, t
ENCH
; these specifications are shown in the data tables and timing diagrams. Encode duty cycle
should be kept as close to 50% as possible.
4
Encode pulse low directly affects the amount of settling time available at FLT resonant port. See External Analog (Resonant) Filter section for details.
5
The 2
×
Clock is generated internally, therefore some specifications are functions of encode period and duty cycle. All timing measurements to or from CLK2
×
are
referenced to 2.0 V crossing.
6
This specification IS a function of Encode period and duty cycle; reference timing diagrams Figure 8.
7
Output rise time is measured from 20% point to 80% point of total CLK2
×
voltage swing; output fall time is measured from 80% point to 20% point of total CLK2
×
voltage swing.
8
Output rise time is measured from 20% point to 80% point of total data voltage swing; output fall time is measured from 80% point to 20% point of total data voltage
swing. All outputs specified with 10 pF load.
Specifications subject to change without notice.
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AD660AR 功能描述:IC DAC 16BIT MONO W/VREF 24-SOIC RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:DACPORT® 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k
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