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参数资料
| 型号： | AD6600ST |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Dual Channel, Gain-Ranging ADC with RSSI |
| 中文描述： | 双通道，增益测距型ADC的RSSI |
| 文件页数： | 4/24页 |
| 文件大小： | 303K |
| 代理商： | AD6600ST |
REV. 0
–4–
AD6600–SPECIFICATIONS
TIMING REQUIREMENTS AND SWITCHING SPECIFICATIONS
1, 2
(AVCC = 5 V, DVCC = 3.3 V; ENC and
ENC
= 20 MSPS, Duty Cycle = 50%; T
MIN
= –40 C, T
MAX
= +85 C unless otherwise noted.)
Test
Level
AD6600AST
Typ
Parameter
ENCODE/CLK2
×
Encode Rising to CLK2
×
Falling
3
Encode Rising to CLK2
×
Rising
4
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle
CLK2
×
/DATA (D10:0, RSSI2:0)
5
CLK2
×
to DATA Rising Low Delay
3
CLK2
×
to DATA Hold Time
3
CLK2
×
to DATA Falling Low
3, 6
Name
Temp
Min
Max
Unit
t
CF
t
CR
Full
Full
Full
Full
IV
IV
IV
IV
6.5
8.0
t
CF
+ (t
ENCH
)/2
27.2
20.5
9.5
ns
ns
ns
ns
25.7
19.0
28.7
22.0
t
2
×
_DRL
t
H_D2
×
t
2
×
_DFL
Full
Full
25
°
C
Full
Full
Full
25
°
C
Full
IV
IV
IV
IV
IV
IV
IV
IV
3.0
3.0
10.0
11.0
6.5
6.5
15.0
15.5
t
ENCH
– t
2
×
_DFL
23.0
10.0
9.5
ns
ns
ns
ns
ns
ns
ns
ns
20.0
22.0
CLK2
×
to DATA Setup Time
4
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle
6
t
S_D2
×
16.5
5.0
3.0
CLK2
×
/AB_OUT
5
CLK2
×
to AB_OUT Rising Low Delay
3
CLK2
×
to AB_OUT Hold Time
3
CLK2
×
to AB_OUT Falling Low Delay
3, 6
t
2
×
_ARL
t
H_A2
×
t
2
×
_AFL
Full
Full
25
°
C
Full
Full
Full
25
°
C
Full
IV
IV
IV
IV
IV
IV
IV
IV
7.0
7.0
12.0
10.7
11.0
11.0
18.0
19.0
t
ENCH
– t
2
×
_AFL
19.5
7.0
6.0
ns
ns
ns
ns
ns
ns
ns
ns
23.0
26.0
CLK2
×
to AB_OUT Setup Time
4
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle
6
t
S_A2
×
12.5
2.0
–1.0
ENCODE/DATA (D10:0, RSSI2:0)
ENCODE to DATA Rising Low Delay
4
ENCODE to DATA Hold Time
4
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle
ENCODE to DATA Falling Low Delay
4
ENCODE to DATA Delay (Setup)
4
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle
6
t
EN_DRL
t
H_DEN
Full
Full
Full
Full
Full
Full
Full
25
°
C
Full
IV
IV
IV
IV
IV
IV
IV
IV
IV
t
CR
+ t
2
×
_DRL
t
EN_DRL
33.7
27.0
t
CR
+ t
2
×
_DFL
t
ENC
– t
EN_DFL
34.2
14.5
14.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
28.7
22.0
t
EN_DFL
t
S_DEN
26.2
8.0
6.0
ENCODE/AB_OUT
ENCODE to AB_OUT Rising Low Delay
4
ENCODE to AB_OUT Delay (Hold)
4
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle
ENCODE to AB_OUT Falling Low Delay
4
ENCODE to AB_OUT Delay (Setup)
4
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle
6
t
EN_ARL
t
H_AEN
Full
Full
Full
Full
Full
Full
Full
25
°
C
Full
IV
IV
IV
IV
IV
IV
IV
IV
IV
t
CR
+ t
2
×
_ARL
t
EN_ARL
38.2
31.5
t
CR
+ t
2
×
_AFL
t
ENC
– t
EN_AFL
30.7
11.5
10.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
32.7
26.0
t
EN_AFL
t
S_AEN
22.2
5.0
2.0
NOTES
1
See AD6600 Timing Diagrams.
2
All switching specifications tested by driving ENC and
ENC
differentially.
3
This specification IS NOT a function of Encode period and duty cycle.
4
This specification IS a function of Encode period and duty cycle.
5
CLK2
×
referenced to 2.0 V crossing; digital output levels referenced to 0.8 V and 2.0 V crossings; all outputs with 10 pF load.
6
For these particular specifications, the 25
°
C specification is valid from 25
°
C to 85
°
C. The Full temperature specification includes cold temperature extreme and
covers the entire range, –40
°
C to +85
°
C.
Specifications subject to change without notice.
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