- 您现在的位置：买卖IC网 > PDF目录373890 > AD6620 (ANALOG DEVICES INC) 65 MSPS Digital Receive Signal Processor(采样速率65MSPS的数字接收信号处理器) PDF资料下载
参数资料
| 型号： | AD6620 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | 65 MSPS Digital Receive Signal Processor(采样速率65MSPS的数字接收信号处理器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP80 |
| 封装： | PLASTIC, QFP-80 |
| 文件页数： | 27/43页 |
| 文件大小： | 388K |
| 代理商： | AD6620 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页当前第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页
AD6620
–27–
REV. 0
If the AD6620s to be synchronized have identical decimation,
then latency through the filter stages will be matched and output
data rates for the Sync master’s filter stages will match the cor-
responding filter stages of the slave.
SYNC M/S
MASTER
SLAVE
SYNC CIC
SYNC RCF
MASTER
SLAVE
Figure 47. SYNC_CIC, SYNC_RCF Pins
The three SYNC inputs to the control block originate from the
same three bidirectional pads from which the three SYNC out-
puts are driven. When the AD6620 is a SYNC MASTER, the
internal circuitry that generates the SYNC pulse outputs is
enabled to the pads. When the AD6620 is a SYNC SLAVE, the
internally produced SYNC pulses are three-stated, and the pads
are driven from an external input. The capacitance on these pins
must be closely monitored since the master responds to the
same SYNC pulse as the slave (its own pulse). There is no input
requirement to the relative phases of these SYNC pulses. In the
absence of SYNC pulses each state machine will free run so the
latter decimation filters can be reliably synchronized by the
SYNC pulses of an earlier stage. However, when sync pulses are
provided externally, setup-and-hold times must be met for each
respective input.
CONTROL REGISTERS AND ON-CHIP RAM
The AD6620 provides a choice of two control ports. It has an 8-
bit generic microprocessor port that is used for configuring the
device at boot up and dynamically reconfiguring the AD6620 in
the system. It also has a synchronous serial port that can also
dynamically reconfigure the AD6620 for the desired system
operation. All control registers are available from both the serial
port and the microprocessor port. These control methods are
nonexclusive and the two ports can be used simultaneously. If
simultaneous access occurs, the serial port is given precedence
over the microprocessor port unless a micro cycle is already
under way. The microprocessor port deasserts the or RDY
signal and waits until the serial access is completed. Output data
is also available from the serial port; this feature is described in
detail in the Serial Port Control section. The mapping of the
AD6620 internal registers is provided below.
Table VI. Control Register and RAM Addresses
Address
000–0FF
100–1FF
200–27F
300
Bit Width
20
36
0
8
Name
RCF Coefficient RAM
RCF Data RAM
Reserved
MODE CONTROL REGISTER
Notation
Description
RCF Coefficient RAM
RCF Data RAM
Reserved
0: SOFT_RESET
1
1: Diversity Channel Real Input Mode
2: Single Channel Complex Input Mode
3: Sync Master/Slave
2
(Master = 1,
Slave = 0)
7–4: Reserved
0: NCO Bypass (Bypass = 1, Active= 0)
1: Enable Phase Dither
2: Enable Amplitude Dither
7–3: Reserved
Write: Sync Mask Shadow
Read: Sync Mask
Channel Frequency for NCO Tuning
NCO Phase Offset
2–0: S
CIC2
3: Reserved
4: ExpInv
7–5: : ExpOff
CIC2 Decimation Minus One
4–0: S
CIC5
7–5: Reserved
CIC5 Decimation Minus One
2–0: Output Scale Factor
7–3: Reserved
RCF Decimation Minus One
Filter Coefficient Address Offset
Number of Taps Minus One
Reserved (Should Be Written 0)
301
3
NCO CONTROL REGISTER
302
32
NCO SYNC CONTROL REGISTER
SYNC_MASK
303
304
305
32
16
8
NCO_FREQ
NCO PHASE_OFFSET
INPUT/CIC2 SCALE REGISTER
NCO_FREQ
306
307
8
5
M
CIC2
– 1
CIC5 SCALE REGISTER
M
CIC2
– 1
S
CIC5
308
309
8
4
M
CIC5
– 1
OUTPUT/RCF CONTROL REGISTER
M
CIC5
– 1
S
OUT
30A
30B
30C
30D
8
8
8
8
M
RCF
– 1
RCF ADDRESS OFFSET REGISTER
N
TAPS
– 1
Reserved (Should Be Written 0)
M
RCF
– 1
RCF
OFF
N
TAPS
– 1
NOTES
1
This bit is set high on
RESET
. The chip is held into SOFT_RESET until it is written low.
2
This bit is set low on
RESET
. This keeps multiple AD6620 SYNC Masters from driving each other.
相关PDF资料 |
PDF描述 |
|---|---|
| AD6622AS | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622PCB | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622S | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622 | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6623 | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6620_01 | 制造商:AD 制造商全称:Analog Devices 功能描述:67 MSPS Digital Receive Signal Processor |
| AD6620AS | 制造商:Analog Devices 功能描述:Signal Processor 80-Pin PQFP 制造商:Rochester Electronics LLC 功能描述:DUAL CHANNEL DECIMATING RECEIVER - Bulk 制造商:Analog Devices 功能描述:IC SIGNAL PROCESSOR |
| AD6620AS-REEL | 制造商:Analog Devices 功能描述:Signal Processor 80-Pin PQFP T/R |
| AD6620ASZ | 功能描述:IC DGTL RCVR DUAL 67MSPS 80-PQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD6620ASZ-REEL | 功能描述:IC DGTL RCVR DUAL 67MSPS 80-PQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
发布紧急采购，3分钟左右您将得到回复。