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参数资料
| 型号： | AD6620 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | 65 MSPS Digital Receive Signal Processor(采样速率65MSPS的数字接收信号处理器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP80 |
| 封装： | PLASTIC, QFP-80 |
| 文件页数： | 36/43页 |
| 文件大小： | 388K |
| 代理商： | AD6620 |
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AD6620
–36–
REV. 0
SDFE
Serial Data Frame End output. SDFE will go high during the
last SCLK cycle of an active time-slot. The SDFE output of a
master AD6620 can be tied to the input SDFS of an AD6620 in
Serial Cascade Mode in order to provide a hardwired time-slot
scenario. When the Last Bit of SDO data is shifted out of the
Master AD6620, the SDFE signal will be driven high by the
same SCLK rising edge that this bit is clocked out on. On the
falling edge of this SCLK cycle, the Cascaded AD6620 will
sample its SDFS signal, which is hardwired to the SDFE of the
Master. On the very next SCLK edge, A channel: I data of the
Cascaded AD6620 will start shifting out of the port. There will
be no rest between the time-slots of the master and slave.
WL[1:0]
WL defines the Word Length of the serial data stream. The
possible options are 00–6 bit words, 01–24 bit words, 10–32 bit
words and 11–Undefined. This setting controls the width of all
serial words. All words are shifted MSB first and are left justi-
fied, i.e., the first n-bits are valid and any padding that is needed
to fill the word length is added at the end. When the serial word
length is 24 or 32 bits, the I and Q output data is presented with
23-bit resolution.
Table XIV. Setting Serial Word Length
Serial Word Length
WL1
WL0
16-Bit
24-Bit
32-Bit
Disallowed
0
0
1
1
0
1
0
1
AD
Append Data signal. In Single Channel Real Mode, when AD is
low the serial data stream consists only of A channel: I and Q
data. If the AD6620 is in Diversity Channel Real Mode, the
serial frame is four words long and consists of both A and B
channel complex data. When the AD signal is high, an extra
serial word is appended to the Serial Frame. This word consists
of any data that is read from the AD6620 internal registers via
the Serial Port. If a Read has not occurred, the data in this word
is zero. The addition of this word allows a Serial System to be
designed so that any AD6620 can have data read at any time
without changing the fixed timing of the serial port.
If the serial transfer includes a register read, the register data is
appended to the serial frame regardless of the state of the AD
pin.
SDIV[3:0]
When the AD6620 is used as a Serial Bus Master the chip gen-
erates a serial clock by dividing down the CLK signal. The
divider ratio is set by the serial division word, SDIV. SDIV is
interpreted as a 4-bit unsigned integer and determines the fre-
quency of the serial clock when the SBM pin is pulled high.
When the AD6620 is in Serial Cascade Mode these bits are
ignored. The following equations express the Serial Clock Fre-
quency as a function of the CLK signal and the SDIV nibble.
f
f
SDIV
f
f
SDIV
SDIV
SCLK
CLK
2
SCLK
CLK
=
=
=
×
≠
0
2
0
,
,
Serial Port Guidelines
The serial clock, SCLK, must be run at a rate sufficient to clock
all of the serial data out of the port before new data is latched
into the internal I and Q data registers. See the Serial Output
Data Port section for more details. If the serial port is to be used
as a means of programming the part, some extra serial band-
width may also be required to shift data from the internal regis-
ters of the AD6620. When used as a serial bus master SCLK
can run at a maximum rate of half the processing CLK. The
equations below help determine what the minimum serial clock
rate must be in order to insure that data is not lost.
f
f
WL
N
R
M
M
M
M
M
SCLK
SAMP
CH
D
TOT
TOT
CIC
CIC
RCF
=
×
×
×
+
=
×
×
(
)
2
2
5
R
D
= 1 if AD is asserted or if read operations are used from the
serial port; otherwise
R
D
= 0. This term accounts for the band-
width consumed when data is read from the internal control
registers or memory.
JTAG BOUNDARY SCAN
The AD6620 supports a subset of IEEE Standard 1149.1
specifications. For additional details of the standard, please see
“IEEE Standard Test Access Port and Boundary-Scan
Architecture,” IEEE-1149 publication from IEEE.
The AD6620 has five pins associated with the JTAG interface.
These pins are used to access the on-chip Test Access Port
(TAP) and are listed in the table below.
Table XV.
Pin Name
Description
TRST
TCLK
TMS
TDI
TDO
TAP Reset
Test Clock
TAP Mode Select
Test Data Input
Test Data Output
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6620_01 | 制造商:AD 制造商全称:Analog Devices 功能描述:67 MSPS Digital Receive Signal Processor |
| AD6620AS | 制造商:Analog Devices 功能描述:Signal Processor 80-Pin PQFP 制造商:Rochester Electronics LLC 功能描述:DUAL CHANNEL DECIMATING RECEIVER - Bulk 制造商:Analog Devices 功能描述:IC SIGNAL PROCESSOR |
| AD6620AS-REEL | 制造商:Analog Devices 功能描述:Signal Processor 80-Pin PQFP T/R |
| AD6620ASZ | 功能描述:IC DGTL RCVR DUAL 67MSPS 80-PQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD6620ASZ-REEL | 功能描述:IC DGTL RCVR DUAL 67MSPS 80-PQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
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