参数资料
| 型号： | AD6620ASZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 1/44页 |
| 文件大小： | 0K |
| 描述： | IC DGTL RCVR DUAL 67MSPS 80-PQFP |
| 标准包装： | 1 |
| 接口： | 并行/串行 |
| 电源电压： | 3 V ~ 3.6 V |
| 封装/外壳： | 80-BQFP |
| 供应商设备封装： | 80-PQFP（14x14） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
| 产品目录页面： | 551 (CN2011-ZH PDF) |
当前第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD6620
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2001
67 MSPS Digital Receive
Signal Processor
FUNCTIONAL BLOCK DIAGRAM
REAL,
DUAL REAL,
OR COMPLEX
INPUTS
SERIAL OR
PARALLEL
OUTPUTS
CIC
FILTERS
OUTPUT
FORMAT
COMPLEX
NCO
P
OR SERIAL
CONTROL
I
Q
–SIN
COS
EXTERNAL
SYNC
CIRCUITRY
JTAG
PORT
II
QQ
FIR
FILTER
AD6620
FEATURES
High Input Sample Rate
67 MSPS Single Channel Real
33.5 MSPS Diversity Channel Real
33.5 MSPS Single Channel Complex
NCO Frequency Translation
Worst Spur Better than –100 dBc
Tuning Resolution Better than 0.02 Hz
2nd Order Cascaded Integrator Comb FIR Filter
Linear Phase, Fixed Coefficients
Programmable Decimation Rates: 2, 3 . . . 16
5th Order Cascaded Integrator Comb FIR Filter
Linear Phase, Fixed Coefficients
Programmable Decimation Rates: 1, 2, 3 . . . 32
Programmable Decimating RAM Coefficient FIR Filter
Up to 134 Million Taps per Second
256 20-Bit Programmable Coefficients
Programmable Decimation Rates: 1, 2, 3 . . . 32
Bidirectional Synchronization Circuitry
Phase Aligns NCOs
Synchronizes Data Output Clocks
Serial or Parallel Baseband Outputs
Pin Selectable Serial or Parallel
Serial Works with SHARC
, ADSP-21xx, Most Other
DSPs
16-Bit Parallel Port, Interleaved I and Q Outputs
Two Separate Control and Configuration Ports
Generic
P Port, Serial Port
3.3 V Optimized CMOS Process
JTAG Boundary Scan
GENERAL DESCRIPTION
The AD6620 is a digital receiver with four cascaded signal-
processing elements: a frequency translator, two fixed-
coefficient decimating filters, and a programmable coefficient
decimating filter. All inputs are 3.3 V LVCMOS compatible.
All outputs are LVCMOS and 5 V TTL compatible.
As ADCs achieve higher sampling rates and dynamic range, it
becomes increasingly attractive to accomplish the final IF stage
of a receiver in the digital domain. Digital IF Processing is less
expensive, easier to manufacture, more accurate, and more
flexible than a comparable highly selective analog stage.
The AD6620 diversity channel decimating receiver is designed
to bridge the gap between high-speed ADCs and general pur-
pose DSPs. The high resolution NCO allows a single carrier to
be selected from a high speed data stream. High dynamic range
decimation filters with a wide range of decimation rates allow
both narrowband and wideband carriers to be extracted. The
RAM-based architecture allows easy reconfiguration for multi-
mode applications.
The decimating filters remove unwanted signals and noise from
the channel of interest. When the channel of interest occupies
less bandwidth than the input signal, this rejection of out-of-
band noise is called “processing gain.” By using large decimation
factors, this “processing gain” can improve the SNR of the
ADC by 36 dB or more. In addition, the programmable RAM
Coefficient filter allows antialiasing, matched filtering, and
static equalization functions to be combined in a single, cost-
effective filter.
The input port accepts a 16-bit Mantissa, a 3-bit Exponent,
and an A/B Select pin. These allow direct interfacing with the
AD6600, AD6640, AD6644, AD9042 and most other high-
speed ADCs. Three input modes are provided: Single Channel
Real, Single Channel Complex, and Diversity Channel Real.
When paired with an interleaved sampler such as the AD6600,
the AD6620 can process two data streams in the Diversity
Channel Real input mode. Each channel is processed with coher-
ent frequency translation and output sample clocks. In addition,
external synchronization pins are provided to facilitate coherent
frequency translation and output sample clocks among several
AD6620s. These features can ease the design of systems with
diversity antennas or antenna arrays.
Units are packaged in an 80-lead PQFP (plastic quad flatpack)
and specified to operate over the industrial temperature range
(–40
°C to +85°C).
SHARC is a registered trademark of Analog Devices, Inc.
相关PDF资料 |
PDF描述 |
|---|---|
| AD6623ASZ | IC TSP 4CHAN 104MSPS 128MQFP |
| AD6641BCPZRL7-500 | IC IF RCVR 11BIT 200MSPS 56LFCSP |
| AD664BJ | IC DAC 12BIT QUAD MONO 44-JLCC |
| AD667BD | IC DAC 12BIT W/BUFF LTCH 28-CDIP |
| AD669BN | IC DAC 16BIT MONO VREF 28-DIP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6620ASZ-REEL | 功能描述:IC DGTL RCVR DUAL 67MSPS 80-PQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD6620PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor |
| AD6620S | 制造商:AD 制造商全称:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor |
| AD6620S/PCB | 制造商:Analog Devices 功能描述:DUAL CHANNEL DECIMATING RECEIV 制造商:Analog Devices 功能描述:SGNL PROCESSOR 169CSPBGA - Bulk |
| AD6622 | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
发布紧急采购，3分钟左右您将得到回复。