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参数资料
| 型号： | AD6620PCB |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 65 MSPS Digital Receive Signal Processor |
| 中文描述： | 65 MSPS的数字接收信号处理器 |
| 文件页数： | 28/43页 |
| 文件大小： | 354K |
| 代理商： | AD6620PCB |
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AD6620
–28–
REV. 0
(0x000–0xFF) RCF COEFFICIENT RAM
Memory that stores user-programmable coefficients for the RCF
filter. The RAM will hold 256 20-bit twos complement words
for a maximum filter length of 256 taps. In Diversity Channel
Real Mode the filter length is limited to 128 taps per channel.
The number of taps used is controlled by N
TAPS
–1 (30C) re-
gardless of the number of coefficient locations programmed. If
filter size allows, more than one filter can be resident in the
memory at a time. This makes it possible to switch filters with-
out reloading all of the coefficients.
(0x100–0x1FF) RCF DATA RAM
These locations store I and Q data exiting the CIC5 filter stage
while the RCF performs multiply accumulates. The lower 18
bits of the 36-bit location is I data; the upper 18 bits are Q data.
These locations are addressed in memory and are available via
the control ports so that the data RAM can be flushed for test-
ing and simulation purposes. They are not cleared on reset.
(0x300) MODE CONTROL REGISTER
This location brings the chip out of reset and sets the operating
mode. It also specifies how the chip will use its SYNC pins: as
outputs while acting as a sync master, or as inputs while acting
as a sync slave. This is the only register with a defined power-up
state: on power-up, Bit 0 will be at a Logic “1.” This places the
chip in SOFT_RESET and defines the chip as a sync slave.
Powering up as a sync slave avoids contention problems when
connecting multiple AD6620s.
If Bit 0 is written low and Bits 2 and 1 are low, the AD6620 is in
Single Channel Real Mode. If Bit 1 is high and Bits 0 and 2 are
low, the device is in the Diversity Channel Real Mode. If Bit 2 is
high and Bits 0 and 1 are low, the chip is in the Single Channel
Complex Mode. Setting Bit 3 high configures the AD6620 as a
SYNC master; the SYNC pins are then used as outputs. If Bit 3
is low, it is a SYNC slave and the SYNC pins function as inputs.
Bits 7–4 are reserved and should be written low.
(0x301) NCO CONTROL REGISTER
This register allows control of special features of the NCO. If
Bit 0 of this register is high the NCO of the AD6620 is by-
passed. Both the I data and the Q data that are passed through
the chip will be the same and the Spectrum will not be trans-
lated. In bypass the input data is attenuated by 12 dB.
The NCO has two features to improve the performance of some
systems: Phase Dither and Amplitude Dither. These can be
used together or alone. If Bit 1 of the register is high, Phase
Dither is activated. If Bit 2 is high, Amplitude Dither is acti-
vated. For more information on dither refer to the NCO section.
(0x302) NCO SYNC CONTROL REGISTER
This holds the SYNC_MASK, which controls the frequency of
the SYNC_NCO pulses and therefore the phase accuracy of the
synchronization. See the NCO section for details.
(0x303) NCO_FREQ
This register holds the NCO frequency control word as de-
scribed in the NCO section. This is a 32-bit unsigned integer
that sets the frequency of the AD6620 NCO.
(0x304) NCO PHASE_OFFSET
This register controls the phase offset of the NCO. It is also
described in detail in the NCO section and can be used to allow
for phase differences between multiple antennas receiving the
same carrier.
(0x305) INPUT/CIC2 SCALE REGISTER
This register holds the scale factor, S
CIC2
, for CIC2. S
CIC2
scales
down the data before it is accumulated in CIC2. This avoids
register wrap-around in the twos-complement arithmetic and
eliminates the resulting spectral errors. S
CIC2
is contained in Bits
2–0 of this register. It is treated as an unsigned integer between
0 and 6. Increasing S
CIC2
shifts data down. For more details
refer to the section on the CIC2 filter.
The second function of this register is to scale the input data
from the Parallel Data Input port. This allows the AD6620 to
treat the floating point input data with considerable flexibility.
There are two parts of this function. The first is Bit 4, which
tells the AD6620 how to handle the exponent, EXP[2:0]. If this
bit is low, data is shifted down as the exponent increases. If this
bit is high, then for increasing EXP[2:0] the input data is shifted
up. The second part of the input data shifting is the Exponent
Offset(ExpOff[7 . . 5]) held in Bits 7–5 of this register. This
provides gain to the input data as described in the Input Port
section.
(0x306) (M
CIC2
– 1)
This register controls the amount of decimation in the CIC2
filter stage. The value contained in this register is the CIC2
decimation rate minus one. This is interpreted as an unsigned
8-bit integer but due to limited growth in the CIC2 filter accu-
mulators this value should be limited to 15 (decimation = 16).
(0x307) S
CIC5
This register holds the scale factor, S
CIC5
, for CIC5. S
CIC5
scales
down the data before it is accumulated in CIC5. This avoids
register wrap-around in the twos-complement arithmetic and
eliminates the resulting spectral errors. S
CIC5
is contained in Bits
4–0 of this register. It is treated as an unsigned integer between
0 and 20. Increasing S
CIC5
shifts data down. For more details
refer to the section on the CIC5 filter.
(0x308) (M
CIC5
– 1)
This register controls the amount of decimation in the CIC5
filter stage. The value contained in this register is the CIC5
decimation rate minus one. This is interpreted as an unsigned
8-bit integer, but due to limited growth in the CIC5 filter accu-
mulators this value should be limited to 31 (decimation = 32).
(0x309) OUTPUT/RCF CONTROL REGISTER
Bits 2-0 of this register hold the Output Scale Factor, S
OUT
.
These bits are interpreted as a 3-bit unsigned integer, the value
of which controls which of the 23 output bits of the RCF are
passed to the output port being used. The data output corre-
sponds to the following equation where OL
RCF
is the 23-bit
output of the RCF and POL is the 16-bit data available at the
parallel output port or the serial port when 16-bit serial words
are used. The truncation function rounds the scaled 23-bit
number to 16 bits. S
OUT
is ignored when WL is 24 or 32 bits. In
most applications, this register should be set to 4 as an initial
starting value.
POL
OL
RCF
(
SOUT
=
×
)
(
–
7
)
2
Bits 7–3 of this register are reserved and must be written 0.
相关PDF资料 |
PDF描述 |
|---|---|
| AD6620AS | 65 MSPS Digital Receive Signal Processor |
| AD6620S | 65 MSPS Digital Receive Signal Processor |
| AD6620 | 65 MSPS Digital Receive Signal Processor(采样速率65MSPS的数字接收信号处理器) |
| AD6622AS | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622PCB | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6620S | 制造商:AD 制造商全称:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor |
| AD6620S/PCB | 制造商:Analog Devices 功能描述:DUAL CHANNEL DECIMATING RECEIV 制造商:Analog Devices 功能描述:SGNL PROCESSOR 169CSPBGA - Bulk |
| AD6622 | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622AS | 制造商:Analog Devices 功能描述:Transmit Signal Processor 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:4 CHANNEL 65 MSPS DIGITAL UPCONVERTER - Bulk |
| AD6622PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
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