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参数资料
| 型号： | AD6622AS |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP128 |
| 封装： | METRIC, QFP-128 |
| 文件页数： | 11/28页 |
| 文件大小： | 242K |
| 代理商： | AD6622AS |
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AD6622
–11–
REV. 0
The serial data frame sync output, SDFS, is pulsed high for one
SCLK cycle at the input sample rate. The input sample rate is
determined by the master clock divided by channel interpolation
factor. If the SCLK rate is not an integer multiple of the input
sample rate, the SDFS will continually adjust the period by one
SCLK cycle in order to keep the average SDFS rate equal to the
input sample rate. When the channel is in sleep mode, SDFS is
held low. The
fi
rst SDFS is delayed by the channel reset latency
after the Channel Reset is removed. The channel reset latency
varies dependent on channel con
fi
guration.
The serial data input, SDIN, accepts 32-bit words as channel
input data. The 32-bit word is interpreted as two 16 bit two
’
s
complement quadrature words, I followed by Q, MSB
fi
rst.
The
fi
rst bit is shifted into the serial port starting on the second
rising edge of SCLK after SDFS goes high, as shown by the
timing diagram below.
CLK
SCLK
SDFS
SDI
CLKn
DATAn
t
DSCLK
t
DSDFS
t
DSDFS
t
SSI
t
HSI
Figure 10. Serial Port Switching Characteristics
As an example of the serial port operation, consider a CLK fre-
quency of 62.208 MSPS and a channel interpolation of 2560.
In that case, the input sample rate is 24.3 kSPS (62.208 MSPS/
2560), which is also the SDFS rate. Substituting, f
SCLK
≥
32
×
f
SDFS
into the equation below and solving for SCLK
DIVIDER
,
we
fi
nd the maximum value for SCLK
DIVIDER
according to
Equation 2.
SCLK
f
DIVIDER
SDFS
≤
×
f
CLK
64
1
–
(2)
Evaluating this equation for our example, SCLK
DIVIDER
must be
less than or equal to 39. Since the SCLK
DIVIDER
channel regis-
ter is a 5-bit unsigned number it can only range from 0 to 31.
Any value in that range will be valid for this example, but if it is
important that the SDFS period is constant, then there is another
restriction. For regular frames, the ratio f
SCLK
/f
SDFS
must be equal
to an integer of 32 or larger. For this example, constant SDFS
periods can only be achieved with an SCLK divider of 19.
In conclusion, the SDFS rate is determined by the AD6622 master
clock rate and the interpolation rate of the channel. The SDFS
rate is equal to the channel input rate. The channel interpola-
tion is equal to RCF interpolation times CIC5 interpolation,
times CIC2 interpolation
L
L
L
L
RCF
CIC
CIC
=
×
×
5
2
(3)
The SCLK rate is determined by the AD6622 master clock
rate and SCLK
DIVIDER
. The SCLK is a divided version of the
AD6622 master CLK. The SCLK divide ratio is determined by
SCLK
DIVIDER
as shown in Equation 2. The SCLK must be fast
enough to input 32 bits of data prior to the next SDFS. Extra
SCLKs are ignored by the serial port.
PROGRAMMABLE INTERPOLATING RAM
COEFFICIENT FILTER (RCF)
Each channel has a fully independent RAM Coef
fi
cient Filter
(RCF). The RCF accepts data from the serial port,
fi
lters it, and
passes the result to the CIC
fi
lter. The RCF implements a FIR
fi
lter with optional interpolation. The FIR
fi
lter can produce
impulse responses up to 128 output samples long. The FIR
response may be interpolated up to a factor of 128, although
the best
fi
lter performance is usually achieved if the RCF inter-
polation factor is con
fi
ned to 8 or below.
FIR Filter Implementation
The RCF accepts quadrature samples from the serial port with a
fi
xed point resolution of 16 bits each, for I and Q.
SERIAL
PORT
DATA
MEM
RCF
RCF COARSE
SCALE
COEFFICIENT
MEM
IQ TO
CIC
FILTER
SDFS
SCLK
SDIN
16,16
ACCUMULATOR
16,16
16,16
Figure 11. RCF Block Diagram
The AD6622 RCF realizes a sum-of-products
fi
lter using a poly-
phase implementation. This mode is equivalent to an interpola-
tor followed by a FIR
fi
lter running at the interpolated rate. In
Figure 12, the interpolating block increases the rate by the RCF
interpolation factor (L
RCF
) by inserting L
RCF
-1 zero valued samples
between every input sample. The next block is a
fi
lter with a
fi
nite
impulse response length (N
RCF
) and an impulse response of h[n],
where n is an integer from 0 to N
RCF
-1.
L
RCF
f
IN
a
b
c
f
IN
L
RCF
N
TAP
FIR FILTER
h[n]
f
IN
L
RCF
Figure 12. RCF Interpolation
The difference equation for Figure 12 is written below, where
h[n] is the RCF impulse response, b[n] is the interpolated input
sample sequence at point
“
b
”
in Figure 12, and c[n] is the out-
put sample sequence at point
“
c
”
in the Figure 12.
[ ]
h k
[
n
[ ]
k
N
RCF
∑
]
=
×
=
0
1
(4)
This difference equation can be described by the transfer func-
tion from point
“
b
”
to
“
c
”
as shown Equation 5.
H
z
h[ ]
z
bc
n
N
n
RCF
=
( )
=
×
0
1
(5)
The actual implementation of this
fi
lter uses a polyphase
decomposition to skip the multiply-accumulates when b[n] is
zero. Compared to the diagram above, this implementation has
the bene
fi
ts of reducing by a factor of L
RCF
both the time needed to
calculate an output and the required data memory (DMEM). The
price of these bene
fi
ts is that the user must place the coef
fi
cients
into the coef
fi
cient memory (CMEM) indexed by the interpo-
lation phase. The process of selecting the coef
fi
cients and placing
them into the CMEM is broken into three steps shown below.
相关PDF资料 |
PDF描述 |
|---|---|
| AD6622PCB | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622S | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622 | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6623 | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623ABC | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6622PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622S | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622S/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6623 | 制造商:Analog Devices 功能描述: |
| AD6623ABC | 制造商:Analog Devices 功能描述:Signal Processor 196-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:4 CHANNEL, 104 MSPS DIGITAL TSP - Bulk |
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