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参数资料
| 型号： | AD6622AS |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP128 |
| 封装： | METRIC, QFP-128 |
| 文件页数： | 17/28页 |
| 文件大小： | 242K |
| 代理商： | AD6622AS |
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AD6622
–17–
REV. 0
SUMMATION BLOCK
The summation block of the AD6622 serves to combine the out-
puts of each channel to create a composite multicarrier signal.
The four channels are summed together and the result is then
added with the 18-bit wideband input bus (IN[17:0]). The
fi
nal
summation is then driven on the 18-bit wideband output bus
(OUT[17:0]) on the rising edge of the high speed clock. If the
OEN input is high, this output bus is three-stated. If the OEN
input is low, this bus will be driven by the summed data. The OEN
is active high to allow the wideband output bus to be connected
to other buses without using extra logic. Most other buses (like
374-type registers) require a low output enable, which is opposite
the AD6622 OEN, thus eliminating extra circuitry.
The wideband output bus may be interpreted as a two
’
s comple-
ment number or as an offset binary number as de
fi
ned by Bit 1
of the Summation Mode Control Register at address 0x000.
When this bit is high, the wideband output is in two's comple-
ment mode and when it is low it is con
fi
gured for offset binary
output data.
The MSB (Bit 17) of the wideband output bus is typically used as
a guard bit for the purpose of clipping the wideband output
bus when Bit 0 of the Summation Mode Control Register at
address 0x000 is high. If clip detection is enabled, Bit 17 of the
output bus is not used as a data bit. Instead, Bit 16 will become the
MSB and be connected to the MSB of the DAC. Con
fi
guring
the DAC in this manner gives the summation block a gain of 0 dB.
When clip detection is not enabled and Bit 17 is used as a data
bit, then the summation block will have a gain of
–
6.02 dB.
There are two data output modes. The
fi
rst is offset binary. This
mode is used only when driving offset binary DACs. Two
’
s comple-
ment mode may be used in one of two circumstances. The
fi
rst is
when driving a DAC that accepts two
’
s complement data. The
second is when driving another AD6622 in cascade mode.
When clipping is enabled, the two
’
s complement mode output
bus will clip to 0x0FFFF for output signals more positive than the
output can express, and it will clip to 0x10000 for signals more
negative than the output can express. In offset binary mode the
output bus will clip to 0x1FFFF for output signals more positive
than the output can express, and it will clip to 0x00000 for signals
more negative than the output can express.
Table VI. Numerical Data Representation
Number Represented
Output Representation
+Full-Scale Two
’
s Complement
–
Full-Scale Two
’
s Complement
+Full-Scale Offset Binary
–
Full-Scale Offset Binary
0x0FFFF
0x10000
0x1FFFF
0x00000
The wideband input is always interpreted as an 18-bit two
’
s
complement number and is typically connected to the wideband
output bus of another AD6622 in order to send more than four
carriers to a single DAC. The Output Bus of the proceeding
AD6622 should be con
fi
gured in two's complement mode and
clip detection disabled. The 18-bit resolution ensures that the
noise and spur performance of the wideband data stream does
not become the limiting factor as large numbers of carriers are
summed.
There is a two-clock cycle latency from the wideband input
bus to the wideband output bus. This latency may be calibrated
out of the system by use of the start hold-off counter. The pre-
ceding AD6622 in a cascaded chain can be started two high-speed
clock cycles before the following AD6622 is started and the data
from each AD6622 will arrive at the DAC on the same clock
cycle. In systems where the individual signals are not corre-
lated, this is usually not necessary.
The AD6622 is capable of outputting both real and complex
data. When in real mode, the QIN input is tied low signaling that
all inputs on the wideband input bus are real and that all outputs
on the wideband output bus are real. The wideband input bus
will be pulled low and no data will be added to the composite
signal if this port is unused (not connected).
If complex data is desired, there are two ways this can be obtained.
The
fi
rst method is simply to set the QIN input of the AD6622
high and set the wideband input bus low. This allows the AD6622
to output complex data on the wideband output bus. The I
data samples would be identi
fi
ed when QOUT is low and the Q
data samples would be identi
fi
ed when QOUT is high. The
second method of obtaining complex data is to provide a QIN
signal that toggles on every rising edge of the high-speed clock.
This could be obtained by connecting the QOUT of another
AD6622 to QIN. In a cascaded system the QIN of the
fi
rst AD6622
in the chain would typically be tied high and the QOUT of the
fi
rst
AD6622 would be connected to the QIN of the following part.
All AD6622s will synchronize themselves to the QIN input so
that the proper samples are always paired and the wideband out-
put bus represents valid complex data samples.
Table VII. QIN, QOUT Functionality
Wideband
Input IN[17:0]
Output Data Type
OUT[17:0]
QIN
QOUT
Low
High
Pulsed
Real
Zero
Complex
Real
Complex
Complex
Low
Pulse
Pulse
TWO'S COMPLEMENT,
CLIPPING DISABLED
AD6622
Q
IN
IN
[17:0]
LOGIC1
LOGIC0
Q
OUT
OUT
[17:0]
AD6622
Q
IN
IN
[17:0]
OUT
[16:3]
14-BIT
DAC
OFFSET BIN,
CLIPPING
ENABLED
Figure 19. Cascade Operation of Two AD6622s
SYNCHRONIZATION
Three types of synchronization can be achieved with the AD6622.
These are Start, Hop, and Beam. Each is described in detail below.
The synchronization is accomplished with the use of a shadow
register and a hold-off counter. See Figure 20 for a simplified
schematic of the NCO Shadow Register and NCO Freq Hold-
Off Counter to understand basic operation. Enabling the clock
(AD6622 CLK) for the Hold-Off Counter can occur with either
a Soft Sync (via the Microport), or a Pin Sync (via the AD6622
sync pin, Pin 62). The functions that include shadow registers
to allow synchronization include:
1. Start
2. Hop (NCO Frequency)
3. Beam (NCO Phase Offset)
相关PDF资料 |
PDF描述 |
|---|---|
| AD6622PCB | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622S | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622 | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6623 | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623ABC | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6622PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622S | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622S/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6623 | 制造商:Analog Devices 功能描述: |
| AD6623ABC | 制造商:Analog Devices 功能描述:Signal Processor 196-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:4 CHANNEL, 104 MSPS DIGITAL TSP - Bulk |
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