- 您现在的位置：买卖IC网 > PDF目录373890 > AD6622AS (ANALOG DEVICES INC) Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP PDF资料下载
参数资料
| 型号： | AD6622AS |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP128 |
| 封装： | METRIC, QFP-128 |
| 文件页数： | 24/28页 |
| 文件大小： | 242K |
| 代理商： | AD6622AS |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页当前第24页第25页第26页第27页第28页
AD6622
–24–
REV. 0
(0x000) Summation Mode Control
Controls functions in the summation block of the AD6622. When
set high, Bit 0 causes the output data to be clipped (no wrap-
around) when overrange of the output occurs. When Bit 0 is low,
overrange will result in wraparound. When set low, Bit 1 formats
the output data as two's complement. Bit 1 set high will for-
mat output data as offset binary.
(0x001) Sync Mode Control
Bits 3
–
0 when high enable synchronization of these channels.
See the Synchronization section of the data sheet for detailed
explanation.
Channel Function Registers
The following registers are channel-speci
fi
c.
“
0x
”
denotes that
these values are represented as hexadecimal numbers.
“
n
”
repre-
sents the speci
fi
ed channel. Valid channels are n = 1, 2, 3, and 4.
(0xn00) Start Update Hold-Off Counter
The Start Update Hold-Off Counter is used to synchronize start
up of AD6622 channels and can be used to synchronize multiple
chips. The Start Update Hold-Off Counter is clocked by the
AD6622 CLK (master clock). See the Synchronization section
of the data sheet for detailed explanation. If no synchronization
is required, this register should be set to 0.
(0xn01) NCO Control
Bit 1:0 set the NCO scaling per the Table XIV.
Table XIV. Control Scale
0x01 Bit 1
0x01 Bit 0
NCO Output Level
0
0
1
1
0
1
0
1
–
6 dB
–
12 dB
–
18 dB
–
24 dB
Bit 2, when high, clears the NCO phase accumulator to 0 on
either a Soft Sync or Pin Sync (see Synchronization for details).
Bit 3, when high, enables NCO phase dither.
Bit 4, when high, enables NCO amplitude dither.
Bits 7:5 are reserved and should be written low.
(0xn02) NCO Frequency
This register is a 32-bit unsigned integer that sets the NCO
Frequency. The NCO Frequency contains a shadow register for
synchronization purposes. The shadow can be read back directly,
the NCO Frequency cannot.
×
NCO
f
CLK
Frequency
channel
=
2
32
(20)
(0xn03) NCO Frequency Update Hold-Off Counter
The Hold-Off Counter is used to synchronize the change of
NCO frequencies. See the Synchronization section of the data
sheet for detailed explanation. If no synchronization is required,
this register should be set to 0.
(0xn04) NCO Phase Offset
This register is a 16-bit unsigned integer that is added to the phase
accumulator of the NCO. This allows phase synchronization of
multiple channels of the AD6622(s). See the Synchronization
section of the data sheet for details. The NCO Phase Offset con-
tains a shadow register for synchronization purposes. The shadow
can be read back directly, the NCO Phase Offset cannot.
(0xn05) NCO Phase Offset Update Hold-Off Counter
The Hold-Off Counter is used to synchronize the change of NCO
phases. See the Synchronization section of the data sheet for
detailed explanation. If no synchronization is required, this
register should be set to 0.
(0xn06) CIC Scale
Bits 5:0 set the CIC scaling per the equation below.
CIC Scale
See CIC section of the data sheet for details. Bits 7:6 are reserved
and should be set to 0.
ceil
L
L
CIC
CIC
_
(log (
))
=
×
5
4
2
(21)
(0xn07) Reserved
This register is reserved and should be set to 0.
(0xn08) CIC2 Interpolation – 1
This register sets the interpolation rate for the CIC2
fi
lter stage
(unsigned integer). The programmed value is the CIC2 Interpo-
lation
–
1. Maximum interpolation is limited by the CIC scaling
available (See CIC section of the data sheet).
(0xn09) CIC5 Interpolation – 1
This register sets the interpolation rate for the CIC5
fi
lter
stage (unsigned integer). The programmed value is the CIC5
Interpolation
–
1. Maximum interpolation is limited by the CIC
scaling available (See CIC section of the data sheet).
(0xn0A) Number of RCF Coefficients – 1
This register sets the number of RCF Coef
fi
cients and is limited
to a maximum of 128. The programmed value is the number of
RCF Coef
fi
cients
–
1.
(0xn0B) RCF Coefficient Offset
This register sets the offset for RCF Coef
fi
cients and is normally
set to 0. It can be viewed as a pointer that selects the portion of
the CMEM used when computing the RCF
fi
lter. This allows
multiple
fi
lters to be stored in the coef
fi
cient memory space,
selecting the appropriate
fi
lter by setting the offset.
(0xn0C) Channel Mode Control 1
Bits 3:0 set N
RCF
/L
RCF
-1.
Bits 5:4 set the channel input format as shown below.
Table XV. Filter Mode
Bit 5
Bit 4
Input Mode
0
0
1
1
0
1
0
1
FIR
Reserved
Reserved
Reserved
Bit 6 Reserved.
Bit 7 Reserved.
(0xn0D) Channel Mode Control 2
Bits 4:0 set the SCLK
DIVIDER
which determines the serial clock
frequency based on the following equation.
f
CLK
SCLK
(
SCLK
DIVIDER
=
×
+
2
1
)
(22)
相关PDF资料 |
PDF描述 |
|---|---|
| AD6622PCB | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622S | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622 | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6623 | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623ABC | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6622PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622S | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622S/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6623 | 制造商:Analog Devices 功能描述: |
| AD6623ABC | 制造商:Analog Devices 功能描述:Signal Processor 196-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:4 CHANNEL, 104 MSPS DIGITAL TSP - Bulk |
发布紧急采购，3分钟左右您将得到回复。