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| 型号： | AD7262BSTZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/33页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT W/PGA&COM 48-LQFP |
| 标准包装： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 120mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 标准包装 |
| 输入数目和类型： | 2 个差分，单极 |
| 产品目录页面： | 777 (CN2011-ZH PDF) |
| 其它名称： | AD7262BSTZ-RL7DKR |
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AD7262
Rev. 0 | Page 15 of 32
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7262/AD7262-5 are fast, dual, simultaneous sampling,
differential, 12-bit, serial ADCs. The AD7262/ AD7262-5
contain two on-chip differential programmable gain amplifiers,
two track-and-hold amplifiers, and two successive approxima-
tion analog-to-digital converters with a serial interface with two
separate data output pins. The AD7262/ AD7262-5 also include
four on-chip comparators. They are housed in 48-lead LFCSP
and LQFP packages, offering the user considerable space-saving
advantages over alternative solutions. The AD7262/AD7262-5
require a low voltage 5 V ± 5% AVCC to power the ADC core and
supply the digital power, a 5.25 V to 2.7 V CA_CBVCC, CC_CDVCC
supply for the comparators, and a 2.7 V to 5.25 V VDRIVE supply
for interface power.
The on-board PGA allows the user to select from 14 program-
mable gain stages: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32,
×48, ×64, ×96, and ×128. The PGA accepts fully differential
analog signals. The gain can be selected either by setting the
logic state of the G0 to G3 pins or by programming the control
register.
The serial clock input accesses data from the part while also
providing the clock source for each successive approximation
ADC. The AD7262/AD7262-5 have an on-chip 2.5 V reference
that can be disabled when an external reference is preferred. If
the internal reference is used elsewhere in a system, the output
from VREFA and VREFB must first be buffered. If the internal
reference is the preferred option, the user must tie the
REFSEL pin to a logic high voltage. Alternatively, if REFSEL
is tied to GND, an external reference can be supplied to both
section).
The AD7262/AD7262-5 also feature a range of power-down
options to allow the user great flexibility with the independent
circuit components while allowing for power savings between
conversions. The power-down feature is implemented via the
control register or the PD0 to PD2 pins, as described in the
Control Register section.
COMPARATORS
The AD7262/AD7262-5 have four on-chip comparators. Com-
parator A and Comparator B have ultralow power consumption,
with static power consumption typically less than 10 μW with a
3.3 V supply. Comparator C and Comparator D feature very fast
propagation delays of 130 ns for a 200 mV differential overdrive.
These comparators have push-pull output stages that operate
from the VDRIVE supply. This feature allows operation with a
minimum amount of power consumption.
Each pair of comparators operates from its own independent
supply, CA_CBVCC and CC_CDVCC. The comparators are specified
for supply voltages from 2.7 V to 5.25 V. If desired, CA_CBVCC
and CC_CDVCC can be tied to the AVCC supply. The four compa-
rators on the AD7262/AD7262-5 are functional with CA_CBVCC/
CC_CDVCC greater than or equal to 1.8 V. However, no specifica-
tions are guaranteed for comparator supplies less than 2.7 V.
The wide range of supply voltages ensures that the comparators
can be used in a variety of battery backup modes.
The four on-chip comparators on the AD7262/AD7262-5 are
ideally suited for monitoring signals from pole sensors in motor
control systems. The comparators can be used to monitor
signals from Hall effect sensors or the inner tracks from an
optical encoder. One of the comparators can be used to count
the index marker or z marker, which is used on startup to place
the motor in a known position.
OPERATION
The AD7262/AD7262-5 have two successive approximation
ADCs, each based around two capacitive DACs and two
programmable gate amplifiers.
The ADC itself comprises control logic, a SAR, and two capacitive
DACs. The control logic and the charge redistribution DACs are
used to add and subtract fixed amounts of charge from the sam-
pling capacitor amplifiers to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code.
Each ADC is preceded by its own programmable gain stage. The
PGA features high analog input impedance, true differential analog
inputs that allow the output from any source or sensor to be
connected directly to the PGA inputs without any requirement for
additional external buffering. The variable gain settings ensure
that the device can be used for amplifying signals from a variety
of sources. The AD7262/AD7262-5 offer the flexibility to choose
the most appropriate gain setting to use the wide dynamic range
of the device.
ANALOG INPUTS
Each ADC in the AD7262/AD7262-5 has two high impedance
differential analog inputs. Figure 24 shows the equivalent circuit
of the analog input structure of the AD7262/AD7262-5. It consists
of a fully differential input amplifier that buffers the analog input
signal and provides the gain selected by using the gain pins or
the control register.
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