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参数资料
| 型号： | AD7265BSUZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/29页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 3CHAN 1MSPS 32TQFP |
| 设计资源： | AD7265 in Differential and Single-Ended Configurations Using AD8022 (CN0048) |
| 标准包装： | 500 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 21mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-TQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 12 个单端，单极；6 个差分，单极；6 个伪差分，单极 |
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AD7265
Rev. A | Page 21 of 28
SCLK
DOUTA
DOUTB
INVALID DATA
VALID DATA
1
10
14
1
THE PART BEGINS
TO POWER UP.
THE PART IS FULLY POWERED UP,
SEE POWER-UP TIMES SECTION.
tPOWER-UP2
CS
04674-
033
Figure 38. Exiting Full Power-Down Mode
POWER-UP TIMES
As described in detail, the AD7265 has two power-down
modes, partial power-down and full power-down. This section
deals with the power-up time required when coming out of
either of these modes. It should be noted that the power-up
times, as explained in this section, apply with the recommended
capacitors in place on the DCAPA and DCAPB pins.
To power up from full power-down (whether using an internal
or external reference), approximately 1.5 ms should be allowed
Powering up from partial power-down requires much less time.
The power-up time from partial power-down is typically 1 μs;
however, if using the internal reference, then the AD7265 must
be in partial power-down for at least 67 μs in order for this
power-up time to apply.
When power supplies are first applied to the AD7265, the ADC
may power up in either of the power-down modes or normal
mode. Because of this, it is best to allow a dummy cycle to
elapse to ensure the part is fully powered up before attempting a
valid conversion. Likewise, if it is intended to keep the part in
the partial power-down mode immediately after the supplies are
applied, then two dummy cycles must be initiated. The first
dummy cycle must hold CS low until after the 10th SCLK falling
edge (see Figure 34); in the second cycle, CS must be brought
high before the 10th SCLK edge but after the second SCLK
falling edge (see Figure 35). Alternatively, if it is intended to
place the part in full power-down mode when the supplies are
applied, then three dummy cycles must be initiated. The first
dummy cycle must hold CS low until after the 10
th SCLK falling
edge (see Figure 34); the second and third dummy cycles place
the part in full power-down (see Figure 37).
Once supplies are applied to the AD7265, enough time must be
allowed for any external reference to power up and charge the
various reference buffer decoupling capacitors to their final values.
POWER vs. THROUGHPUT RATE
The power consumption of the AD7265 varies with throughput
rate. When using very slow throughput rates and as fast an
SCLK frequency as possible, the various power-down options
can be used to make significant power savings. However, the
AD7265 quiescent current is low enough that even without
using the power-down options, there is a noticeable variation in
power consumption with sampling rate. This is true whether a
fixed SCLK value is used or if it is scaled with the sampling rate.
rate when operating in normal mode for a fixed maximum
SCLK frequency, and an SCLK frequency that scales with the
sampling rate with VDD = 3 V and VDD = 5 V, respectively. In all
cases, the internal reference was used.
04
67
4-
0
45
THROUGHPUT (kSPS)
1000
0
100
200
300
500
400
700
800
900
600
P
O
WE
R
(
m
W)
10.0
9.0
8.5
9.5
8.0
7.0
6.5
7.5
6.0
5.5
5.0
16MHz SCLK
VARIABLE SCLK
TA = 25°C
Figure 39. Power vs. Throughput in Normal Mode with VDD = 3 V
04674-046
THROUGHPUT (kSPS)
1000
0
200
300
400
100
500
600
700
800
900
P
O
WE
R
(mW)
25
21
19
23
17
13
15
9
7
11
5
VARIABLE SCLK
TA = 25°C
16MHz SCLK
Figure 40. Power vs. Throughput in Normal Mode with VDD = 5 V
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