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参数资料
| 型号： | AD7265BSUZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/29页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 3CHAN 1MSPS 32TQFP |
| 设计资源： | AD7265 in Differential and Single-Ended Configurations Using AD8022 (CN0048) |
| 标准包装： | 500 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 21mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-TQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 12 个单端，单极；6 个差分，单极；6 个伪差分，单极 |
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AD7265
Rev. A | Page 23 of 28
MICROPROCESSOR INTERFACING
The connection diagram is shown in
The serial interface on the AD7265 allows the part to be directly
connected to a range of many different microprocessors. This
section explains how to interface the AD7265 with some of the
more common microcontroller and DSP serial interface
protocols.
Figure 43. The ADSP-218x
has the TFS0 and RFS0 of the SPORT0 and the RFS1 of
SPORT1 tied together. TFS0 is set as an output, and both RFS0
and RFS1 are set as inputs. The DSP operates in alternate
framing mode, and the SPORT control register is set up as
described. The frame synchronization signal generated on the
TFS is tied to
AD7265 TO ADSP-218x
CS, and, as with all signal processing applications,
equidistant sampling is necessary. However, in this example, the
timer interrupt is used to control the sampling rate of the ADC
and, under certain conditions, equidistant sampling may not be
achieved.
The ADSP-218x family of DSPs interface directly to the
AD7265 without any glue logic required. The VDRIVE pin of the
AD7265 takes the same supply voltage as that of the ADSP-218x.
This allows the ADC to operate at a higher supply voltage than
its serial interface and, therefore, the ADSP-218x, if necessary.
This example shows both D
AD72651
SCLK
CS
ADSP-218x1
1ADDITIONAL PINS OMITTED FOR CLARITY.
SCLK0
DR0
RFS0
TFS0
DOUTA
VDRIVE
VDD
DOUTB
DR1
RFS1
SCLK1
04
67
4-
0
36
A and D
OUT
B of the AD7265
connected to both serial ports of the ADSP-218x. The SPORT0
and SPORT1 control registers should be set up as shown in
Table 7. SPORT0 Control Register Setup
Setting
Description
TFSW = RFSW = 1
Alternate framing
INVRFS = INVTFS = 1
Active low frame signal
DTYPE = 00
Right justify data
SLEN = 1111
16-bit data-word (or may be set to
1101 for 14-bit data-word)
ISCLK = 1
Internal serial clock
TFSR = RFSR = 1
Frame every word
Figure 43. Interfacing the AD7265 to the ADSP-218x
IRFS = 0
ITFS = 1
The timer registers are loaded with a value that provides an
interrupt at the required sample interval. When an interrupt is
received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS, and hence, the
reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given (AX0 = TX0), the state of the SCLK is checked. The
DSP waits until the SCLK has gone high, low, and high again
before transmission starts. If the timer and SCLK values are
chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, then the data may be transmitted or it
may wait until the next clock edge.
Table 8. SPORT1 Control Register Setup
Setting
Description
TFSW = RFSW = 1
Alternate framing
INVRFS = INVTFS = 1
Active low frame signal
DTYPE = 00
Right justify data
SLEN = 1111
16-bit data-word (or may be set to
1101 for 14-bit data-word)
ISCLK = 0
External serial clock
TFSR = RFSR = 1
Frame every word
IRFS = 0
ITFS = 1
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3,
then an SCLK of 2 MHz is obtained, and eight master clock
periods will elapse for every one SCLK period. If the timer
registers are loaded with the value 803, then 100.5 SCLKs will
occur between interrupts and, subsequently, between transmit
instructions. This situation yields sampling that is not equidistant,
as the transmit instruction is occurring on a SCLK edge. If the
number of SCLKs between interrupts is a whole integer figure
of N, then equidistant sampling will be implemented by the DSP.
To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst.
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