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| 型号： | AD7329BRUZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/41页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT+SAR 8CHAN 24-TSSOP |
| 标准包装： | 1,000 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 30mW |
| 电压电源： | 双 ± |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 8 个单端，单极；8 个单端，双极；4 个差分，单极；4 个差分，双极 |
| 配用： | EVAL-AD7329CBZ-ND - BOARD EVALUATION FOR AD7329CBZ |
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AD7329
Data Sheet
Rev. B | Page 18 of 40
Figure 26 shows the differential configuration during the
acquisition phase. For the conversion phase, SW3 opens and
SW1 and SW2 move to Position B (see Figure 27). The output
impedances of the source driving the VIN+ and VIN pins must
match; otherwise, the two inputs have different settling times,
resulting in errors.
CAPACITIVE
DAC
CONTROL
LOGIC
CAPACITIVE
DAC
COMPARATOR
SW3
SW1
A
B
CS
VIN+
SW2
A
B
VIN–
VREF
05402-
025
Figure 26. ADC Configuration During Acquisition Phase, Differential Mode
CAPACITIVE
DAC
CONTROL
LOGIC
CAPACITIVE
DAC
COMPARATOR
SW3
SW1
A
B
CS
VIN+
SW2
A
B
VIN–
VREF
05402-
026
Figure 27. ADC Configuration During Conversion Phase, Differential Mode
OUTPUT CODING
The AD7329 default output coding is set to twos complement.
The output coding is controlled by the coding bit in the control
register. To change the output coding to straight binary coding,
the coding bit in the control register must be set. When
operating in sequence mode, the output coding for each
channel in the sequence is the value written to the coding bit
during the last write to the control register.
TRANSFER FUNCTIONS
The designed code transitions occur at successive integer LSB
values (that is, 1 LSB, 2 LSB, and so on). The LSB size is
dependent on the analog input range selected.
Table 7. LSB Sizes for Each Analog Input Range
Input Range
Full-Scale Range/8192 Codes
LSB Size
±10 V
20 V
2.441 mV
±5 V
10 V
1.22 mV
±2.5 V
5 V
0.61 mV
0 V to +10 V
10 V
1.22 mV
The ideal transfer characteristic for the AD7329 when twos
complement coding is selected is shown in Figure 28. The ideal
transfer characteristic for the AD7329 when straight binary
coding is selected is shown in Figure 29.
011 ... 111
011 ... 110
000 ... 001
000 ... 000
111 ... 111
–FSR/2 + 1LSB
AGND + 1LSB
+FSR/2 – 1LSB BIPOLAR RANGES
+FSR – 1LSB
UNIPOLAR RANGE
AGND – 1LSB
ANALOG INPUT
ADC
CO
DE
100 ... 010
100 ... 001
100 ... 000
05402-
027
Figure 28. Twos Complement Transfer Characteristic, Bipolar Ranges
111 ... 111
111 ... 110
111 ... 000
011 ... 111
–FSR/2 + 1LSB
AGND + 1LSB
+FSR/2 – 1LSB BIPOLAR RANGES
+FSR – 1LSB
UNIPOLAR RANGE
ANALOG INPUT
ADC
CO
DE
000 ... 010
000 ... 001
000 ... 000
05402-
028
Figure 29. Straight Binary Transfer Characteristic, Bipolar Ranges
ANALOG INPUT STRUCTURE
The analog inputs of the AD7329 can be configured as single-
ended, true differential, or pseudo differential via the control
register mode bits, as shown in Table 12. The AD7329 can accept
true bipolar input signals. On power-up, the analog inputs operate
as eight single-ended analog input channels. If true differential
or pseudo differential is required, a write to the control register
is necessary after power-up to change this configuration.
Figure 30 shows the equivalent analog input circuit of the
AD7329 in single-ended mode. Figure 31 shows the equivalent
analog input structure in differential mode. The two diodes
provide ESD protection for the analog inputs.
D
VDD
ADCIN+
MUXOUT+
C2
R1
VIN0
VSS
C1
C3
C4
05402-
029
Figure 30. Equivalent Analog Input Circuit, Single-Ended Mode
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