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| 型号： | AD7329BRUZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 27/41页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT+SAR 8CHAN 24-TSSOP |
| 标准包装： | 1,000 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 30mW |
| 电压电源： | 双 ± |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 8 个单端，单极；8 个单端，双极；4 个差分，单极；4 个差分，双极 |
| 配用： | EVAL-AD7329CBZ-ND - BOARD EVALUATION FOR AD7329CBZ |
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AD7329
Data Sheet
Rev. B | Page 32 of 40
MODES OF OPERATION
The AD7329 has several modes of operation that are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for different application requirements. The mode of
operation of the AD7329 is controlled by the power management
bits, Bit PM1 and Bit PM0, in the control register as shown in
Table 13. The default mode is normal mode, where all internal
circuitry is fully powered up.
NORMAL MODE
(PM1 = PM0 = 0)
This mode is intended for the fastest throughput rate
performance with the AD7329 being fully powered up at all
times. Figure 52 shows the general operation of the AD7329
in normal mode.
The conversion is initiated on the falling edge of CS, and the
track-and-hold section enters hold mode, as described in the
Serial Interface section. The data on the DIN line during the
16 SCLK transfer is loaded into one of the on-chip registers if
the write bit is set. The register is selected by programming the
register select bits (see Table 10).
1
16
3 CHANNEL I.D. BITS, SIGN BIT + CONVERSION RESULT
DATA INTO CONTROL/SEQUENCE/RANGE1/RANGE2
REGISTER
SCLK
CS
DOUT
DIN
05402-
047
Figure 52. Normal Mode
The AD7329 remains fully powered up at the end of the
conversion if both PM1 and PM0 contain 0 in the control
register.
To complete the conversion and access the conversion result,
16 serial clock cycles are required. At the end of the conversion,
CS can idle either high or low until the next conversion.
After the data transfer is complete, another conversion can be
initiated after the quiet time, tQUIET, has elapsed.
FULL SHUTDOWN MODE
(PM1 = PM0 = 1)
In this mode, all internal circuitry on the AD7329 is powered
down. The part retains information in the registers during full
shutdown. The AD7329 remains in full shutdown mode until
the power management bits, Bit PM1 and Bit PM0, in the
control register are changed.
A write to the control register with PM1 = PM0 = 1 places the
part into full shutdown mode. The AD7329 enters full shutdown
mode on the 15th SCLK rising edge when the control register is
updated.
If a write to the control register occurs while the part is in full
shutdown mode with the power management bits, Bit PM1 and
Bit PM0, set to 0 (normal mode), the part begins to power up on
the 15th SCLK rising edge when the control register is updated.
shutdown mode. To ensure that the AD7329 is fully powered
up, tPOWER-UP should elapse before the next CS falling edge.
CS
1
16
1
16
SCLK
SDATA
DIN
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA INTO CONTROL REGISTER
DATA INTO CONTROL/SHADOW REGISTER
tPOWER-UP
THE PART IS FULLY POWERED UP
ONCE
tPOWER-UP HAS ELAPSED
CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS.
PM1 = PM0 = 0
TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 0
IN CONTROL REGISTER
PART IS IN FULL
SHUTDOWN
THE PART BEGINS TO POWER UP ON THE
15TH SCLK RISING EDGE AS PM1 = PM0 = 0
05402-
048
Figure 53. Exiting Full Shutdown Mode
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