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参数资料
| 型号： | AD73311ARS |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Low Cost, Low Power CMOS General Purpose Analog Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO20 |
| 封装： | SSOP-20 |
| 文件页数： | 22/36页 |
| 文件大小： | 382K |
| 代理商： | AD73311ARS |
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REV. A
AD73311L
–22–
FREQUENCY
–
Hz
20
–
1000
7
1
I
2
3
4
5
6
0
–
20
–
40
–
60
–
80
10
4
Figure 23. Codec Uncompensated Input-to-Output
Frequency Response (f
SAMP
= 64 kHz)
In the DAC section, increasing the sampling rate by interpola-
tion creates images of the original waveform at intervals of the
original sampling frequency. These images may be suf
fi
ciently
rejected by external circuitry, but the sinc-cubed
fi
lter in the
interpolator again nulls the output spectrum at integer intervals
of the original sampling rate which corresponds with the images
due to the interpolation process.
The spectral response of a sinc-cubed
fi
lter shows the character-
istic nulls at integer intervals of the sampling frequency. Its
passband characteristic (up to Nyquist frequency) features a
roll-off that continues up to the sampling frequency, where the
fi
rst null occurs. In many applications this smooth response will
not give suf
fi
cient attenuation of frequencies outside the band of
interest, therefore, it may be necessary to implement a
fi
nal
fi
lter
in the DSP which will equalize the passband rolloff and provide
a sharper transition band and greater stopband attenuation.
FREQUENCY
–
Hz
20
–
1000
7
1
I
2
3
4
5
6
0
–
20
–
40
–
60
–
80
10
4
Figure 24. Codec Compensated Input-to-Output
Frequency Response (f
SAMP
= 64 kHz)
DESIGN CONSIDERATIONS
The AD73311L features both differential inputs and outputs on
each channel to provide optimal performance and avoid common-
mode noise. It is also possible to interface either inputs or outputs
in single-ended mode. This section details the choice of input
and output con
fi
gurations and also gives some tips towards
successful con
fi
guration of the analog interface sections.
COTIME
LOW-PASS
FILTER
REFOUT
REFERENCE
V
REF
REFCAP
0.1 F
0/38dB
PGA
+6/
–
15dB
PGA
VINP
VINN
AFILTER
0.047 F
100
0.047 F
100
AD73311L
VOUTP
VOUTN
Figure 25. Analog Input (DC-Coupled)
Analog Inputs
The analog input (encoder) section of the AD73311L can be
interfaced to external circuitry in either ac-coupled or dc-coupled
modes.
It is also possible to drive the ADCs in either differential or
single-ended modes. If the single-ended mode is chosen it is
possible, using software control, to multiplex between two single-
ended inputs connected to the positive and negative input pins.
The primary concerns in interfacing to the ADC are
fi
rstly to
provide adequate antialias
fi
ltering and to ensure that the signal
source will drive the switched-capacitor input of the ADC cor-
rectly. The sigma-delta design of the ADC and its oversampling
characteristics simplify the antialias requirements but it must be
remembered that the single pole RC
fi
lter is primarily intended
to eliminate aliasing of frequencies above the Nyquist frequency of
the sigma-delta modulator
’
s sampling rate (typically 2.048 MHz).
It may still require a more speci
fi
c digital
fi
lter implementa-
tion in the DSP to provide the
fi
nal signal frequency response
characteristics. It is recommended that for optimum performance
the capacitors used for the antialiasing
fi
lter be of high quality
dielectric (NPO). The second issue mentioned above is interfacing
the signal source to the ADC
’
s switched capacitor input load.
The SC input presents a complex dynamic load to a signal
source, therefore, it is important to understand that the slew
rate characteristic is an important consideration when choosing
external buffers for use with the AD73311L. The internal inverting
op amps on the AD73311L are speci
fi
cally designed to interface
to the ADC
’
s SC input stage.
The AD73311L
’
s on-chip 38 dB preampli
fi
er can be enabled
when there is not enough gain in the input circuit; the preampli-
fi
er is con
fi
gured by bits IGS0-2 of CRD. The total gain must be
con
fi
gured to ensure that a full-scale input signal produces a signal
level at the input to the sigma-delta modulator of the ADC that
does not exceed the maximum input range.
相关PDF资料 |
PDF描述 |
|---|---|
| AD73311LAR | Low Cost, Low Power CMOS General Purpose Analog Front End |
| AD73311L | Low Cost, Low Power CMOS General Purpose Analog Front End Processor(低成本，低功耗的CMOS通用双模拟前端处理器) |
| AD73311 | Low Cost, Low Power CMOS General Purpose Analog Front End Processor(低成本、低功耗、CMOS通用模拟前端处理器) |
| AD73322LARU | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| AD73322AR | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73311ARS-REEL | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:SPEECH & TELEPHONY CODEC I.C. - Tape and Reel |
| AD73311ARSZ | 功能描述:IC ANALOG FRONT END 20-SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73311ARSZ-REEL | 功能描述:IC ANALOG FRONT END 20-SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73311ARZ | 功能描述:IC PROCESSOR FRONT END LP 20SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73311ARZ-REEL | 功能描述:IC PROCESSOR FRONT END LP 20SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
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