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参数资料
| 型号： | AD73322AR |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO28 |
| 封装： | SOIC-28 |
| 文件页数： | 14/40页 |
| 文件大小： | 437K |
| 代理商： | AD73322AR |
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REV. 0
AD73322L
–14–
Analog Gain Tap
The analog gain tap is configured as a programmable differential
amplifier whose input is taken from the ADC
’
s input signal
path. The output of the analog gain tap is summed with the
output of the DAC. The gain is programmable using Control
Register F (CRF:0-4) to achieve a gain of
–
1 to +1 in 32 steps
with muting being achieved through a separate control setting
(Control Register F Bit 7). The gain increment per step is 0.0625.
The AGT is enabled by powering-up the AGT control bit in the
power control register (CRC:1). When this bit is set (=1) CRF
becomes an AGT control register with CRF:0-4 holding the
AGT coefficient, CRF:5 becomes an AGT enable and CRF:7
becomes an AGT mute control bit. Control bit CRF:5 connects/
disconnects the AGT output to the summer block at the output
of the DAC section while control bit CRF:7 overrides the gain
tap setting with a mute, (zero gain) setting. Table V shows the
gain versus digital setting for the AGT.
Table V. Analog Gain Tap Settings
*
AGTC4
AGTC3
AGTC2
AGTC1
AGTC0
Gain (dB)
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
1
1
1
0
0
0
0
1
1
0
1
1
1
0
0
1
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
+1.00
+0.9375
+0.875
+0.8125
+0.75
+0.0625
–
0.0625
–
0.875
–
0.9375
–
1.00
*
AGT and DGT weights are given for the case of VFBNx (connected to the
sigma-delta modulator
’
s positive input) being at a higher potential than VFBPx
(connected to the sigma-delta modulator
’
s negative input).
Digital Gain Tap
The digital gain tap features a programmable gain block whose
input is taken from the bitstream output of the ADC
’
s sigma-
delta modulator. This single bit input (1 or 0) is used to add or
subtract a programmable value, which is the digital gain tap setting,
to the output of the DAC section
’
s interpolator. The program-
mable setting has 16-bit resolution and is programmed using the
settings in Control Registers G and H. (See Table VI).
Table VI. Digital Gain Tap Settings
*
DGT15–0 (Hex)
Gain
0x8000
0x9000
0xA000
0xC000
0xE000
0x0000
0x2000
0x4000
0x6000
0x7FFF
–
1.00
–
0.875
–
0.75
–
0.5
–
0.25
0.00
+0.25
+0.05
+0.75
+0.99999
*
AGT and DGT weights are given for the case of VFBNx (connected to the
sigma-delta modulator
’
s positive input) being at a higher potential than VFBPx
(connected to the sigma-delta modulator
’
s negative input).
Serial Port (SPORT)
The codecs communicate with a host processor via the bidirec-
tional synchronous serial port (SPORT), which is compatible
with most modern DSPs. The SPORT is used to transmit and
receive digital data and control information. The dual codec is
implemented using two separate codec blocks that are internally
cascaded with serial port access to the input of Codec1 and the
output of Codec2. This allows other single or dual codec devices to
be cascaded together (up to a limit of eight codec units).
MCLK
DIVIDER
MCLK
EXTERNAL
SE
RESET
SDIFS
SDI
SERIAL PORT 1
(SPORT 1)
SERIAL REGISTER 1
SCLK
DIVIDER
SCLK
CONTROL
REGISTER
1B
CONTROL
REGISTER
1C
CONTROL
REGISTER
1D
CONTROL
REGISTER
1E
CONTROL
REGISTER
1A
CONTROL
REGISTER
1G
CONTROL
REGISTER
1F
CONTROL
REGISTER
1H
3
8
8
8
8
8
16
8
2
DMCLK INTERNAL
MCLK
DIVIDER
MCLK
EXTERNAL
SE
RESET
SDIFS2
SDI2
SERIAL PORT 2
(SPORT 2)
SERIAL REGISTER 2
SCLK
DIVIDER
CONTROL
REGISTER
2B
CONTROL
REGISTER
2C
CONTROL
REGISTER
2D
CONTROL
REGISTER
2E
CONTROL
REGISTER
2A
CONTROL
REGISTER
2G
CONTROL
REGISTER
2F
CONTROL
REGISTER
2H
3
8
8
8
8
8
16
8
2
DMCLK INTERNAL
SDOFS
SDO
SDOFS1
SDO1
Figure 10. SPORT Block Diagram
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相关代理商/技术参数 |
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|---|---|
| AD73322AR-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin SOIC W T/R |
| AD73322AR-REEL7 | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin SOIC W T/R |
| AD73322ARZ | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin SOIC W 制造商:Analog Devices 功能描述:AUD CODEC 2ADC / 2DAC 16BIT 28SOIC - Trays 制造商:Analog Devices 功能描述:Dual Voice Band Codec 16-Bit 3/5V SOIC28 |
| AD73322ARZ-REEL | 制造商:Analog Devices 功能描述:DUAL VOICE BAND ANALOG FRONT END IC (ROHS) - Tape and Reel 制造商:Analog Devices 功能描述:DUAL VOICEBAND ANALOG FRONT END IC |
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