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参数资料
| 型号： | AD73322AR |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO28 |
| 封装： | SOIC-28 |
| 文件页数： | 16/40页 |
| 文件大小： | 437K |
| 代理商： | AD73322AR |
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REV. 0
AD73322L
–16–
Serial Clock Rate Divider
The AD73322L features a programmable serial clock divider
that allows users to match the serial clock (SCLK) rate of the
data to that of the DSP engine or host processor. The maximum
SCLK rate available is DMCLK and the other available rates
are: DMCLK/2, DMCLK/4 and DMCLK/8. The slowest rate
(DMCLK/8) is the default SCLK rate. The serial clock divider
is programmable by setting bits CRB:2
–
3. Table VIII shows the
serial clock rate corresponding to the various bit settings.
Table VIII. SCLK Rate Divider Settings
SCD1
SCD0
SCLK Rate
0
0
1
1
0
1
0
1
DMCLK/8
DMCLK/4
DMCLK/2
DMCLK
Sample Rate Divider
The AD73322L features a programmable sample rate divider
that allows users flexibility in matching the codec
’
s ADC and
DAC sample rates (decimation/interpolation rates) to the needs
of the DSP software. The maximum sample rate available is
DMCLK/256, which offers the lowest conversion group delay,
while the other available rates are: DMCLK/512, DMCLK/
1024 and DMCLK/2048. The slowest rate (DMCLK/2048) is
the default sample rate. The sample rate divider is program-
mable by setting bits CRB:0-1. Table IX shows the sample
rate corresponding to the various bit settings.
Table IX. Sample Rate Divider Settings
DIR1
DIR0
SCLK Rate
0
0
1
1
0
1
0
1
DMCLK/2048
DMCLK/1024
DMCLK/512
DMCLK/256
DAC Advance Register
The loading of the DAC is internally synchronized with the
unloading of the ADC data in each sampling interval. The
default DAC load event happens one SCLK cycle before the
SDOFS flag is raised by the ADC data being ready. However,
this DAC load position can be advanced before this time by
modifying the contents of the DAC advance field in Control
Register E (CRE:0
–
4). The field is five bits wide, allowing 31
increments of weight 1/(F
S
×
32); see Table X. The sample rate
F
S
is dependent on the setting of both the MCLK divider and
the Sample Rate divider; see Tables VII and IX. In certain cir-
cumstances this DAC update adjustment can reduce the group
delay when the ADC and DAC are used to process data in series.
Appendix C details how the DAC advance feature can be used.
NOTE: The DAC advance register should not be changed while
the DAC section is powered up.
Table X. DAC Timing Control
DA4
DA3
DA2
DA1
DA0
Time Advance
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
0
1
0 s
1/(F
S
×
32) s
2/(F
S
×
32) s
30/(F
S
×
32) s
31/(F
S
×
32) s
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相关代理商/技术参数 |
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|---|---|
| AD73322AR-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin SOIC W T/R |
| AD73322AR-REEL7 | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin SOIC W T/R |
| AD73322ARZ | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin SOIC W 制造商:Analog Devices 功能描述:AUD CODEC 2ADC / 2DAC 16BIT 28SOIC - Trays 制造商:Analog Devices 功能描述:Dual Voice Band Codec 16-Bit 3/5V SOIC28 |
| AD73322ARZ-REEL | 制造商:Analog Devices 功能描述:DUAL VOICE BAND ANALOG FRONT END IC (ROHS) - Tape and Reel 制造商:Analog Devices 功能描述:DUAL VOICEBAND ANALOG FRONT END IC |
| AD73322ARZ-REEL7 | 制造商:Analog Devices 功能描述:DUAL VOICEBAND CODEC - Tape and Reel |
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